Author

Vivek Tyagi

Observed name: V. Tyagi
ORCID: 0000-0002-9572-2107
Observed ORCID: 0000-0002-9572-2107
OpenAlex ID: A5065747975
2019 · M. Carissimi, R. Zurla, et al. · European Solid-State Circuits Conference (ESSCIRC) · 9
2022 · Shivam Kalla, Vivek Tyagi, et al. · Analog Integrated Circuits and Signal Processing · 3
2020 · Vivek Tyagi, Shivam Kalla, et al. · Analog Integrated Circuits and Signal Processing · 2
2020 · Vivek Tyagi, Vikas Rana, et al. · International Conference on VLSI Design · 2
2021 · Vivek Tyagi, Shivam Kalla, et al. · International Conference on VLSI Design · 1
2019 · Vivek Tyagi, Vikas Rana, et al. · International Conference on VLSI Design · 1
2021 · Vivek Tyagi, Vikas Rana · International Conference on VLSI Design
2017 · Vivek Tyagi, M. S. Hashmi, et al. · Communications in computer and information science
2017 · Vivek Tyagi, M. S. Hashmi, et al. · Communications in computer and information science
Works count: 11
Citation count: 25
H-index: 3
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