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Author

Junjong Lee

Observed name: LEE, JUNJONG
Institution: Kookmin University
ORCID: 0000-0002-0513-8784
Observed ORCID: 0000-0002-0513-8784
OpenAlex ID: A5066167254
Reduction of Process Variations for Sub-5-nm Node Fin and Nanosheet FETs Using Novel Process Scheme
2020 · Jun-Sik Yoon, Seunghwan Lee, et al. · IEEE Transactions on Electron Devices · 47
Performance, Power, and Area of Standard Cells in Sub 3 nm Node Using Buried Power Rail
2022 · Jun-Sik Yoon, Jinsu Jeong, et al. · IEEE Transactions on Electron Devices · 29
Electrical Coupling Effect of Forksheet FET for Power, Performance, and Area Analysis
2022 · Junjong Lee, Jun-Sik Yoon, et al. · IEEE Transactions on Electron Devices · 27
Source/Drain Patterning FinFETs as Solution for Physical Area Scaling Toward 5-nm Node
2019 · Jun-Sik Yoon, Seunghwan Lee, et al. · IEEE Access · 21
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High-Speed Ternary CMOS Inverter by Monolithic Integration of NbO 2 Threshold Switch with MOSFET
2021 · Seongjae Heo, Junjong Lee, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 18
Investigation of Electrothermal Characteristics in Silicon Forksheet FETs for Sub-3-nm Node
2023 · Jaewan Lim, Jinsu Jeong, et al. · IEEE Transactions on Electron Devices · 16
Sensitivity of Inner Spacer Thickness Variations for Sub-3-nm Node Silicon Nanosheet Field-Effect Transistors
2022 · Sanguk Lee, Jinsu Jeong, et al. · Nanomaterials · 12
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Novel Scheme of Inner Spacer Length Optimization for Sub-3-nm Node Silicon n/p Nanosheet Field-Effect Transistors
2023 · Sanguk Lee, Jinsu Jeong, et al. · IEEE Transactions on Electron Devices · 11
Gate-All-Around FETs: Nanowire and Nanosheet Structure
2020 · Jun-Sik Yoon, Jinsu Jeong, et al. · IntechOpen eBooks · 10
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Novel Modeling Approach to Analyze Threshold Voltage Variability in Short Gate-Length (15–22 nm) Nanowire FETs with Various Channel Diameters
2022 · Seunghwan Lee, Jun-Sik Yoon, et al. · Nanomaterials · 8
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DC Performance Variations by Grain Boundary in Source/Drain Epitaxy of Sub-3-nm Nanosheet Field-Effect Transistors
2022 · Jun-Sik Yoon, Jinsu Jeong, et al. · IEEE Access · 8
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TCAD-Based Flexible Fin Pitch Design for 3-nm Node 6T-SRAM Using Practical Source/Drain Patterning Scheme
2021 · Junjong Lee, Jun-Sik Yoon, et al. · IEEE Transactions on Electron Devices · 8
Novel High-Speed Ternary Logic Using Step-Shaped Threshold Switch
2023 · Junjong Lee, Seongjae Heo, et al. · IEEE Electron Device Letters · 7
Power, Performance, and Area Analysis of Ultra-Stacked Forksheet-FET for Angstrom Nodes
2025 · Junjong Lee, Sanguk Lee, et al. · IEEE Transactions on Electron Devices · 6
BS-PDN Implemented the Latest Logic Devices for 14 Angstrom Technology Node
2024 · Junjong Lee, Stanley Seungchul Song, et al. · IEEE Transactions on Electron Devices · 6
Investigation of Self-Heating Effect in Forksheet FETs for Sub-3-nm Node
2023 · Jaewan Lim, Jinsu Jeong, et al. · IEEE Electron Devices Technology & Manufacturing Conference (EDTM) · 6
Observation of mobility and velocity behaviors in ultra-scaled LG = 15 nm silicon nanowire field-effect transistors with different channel diameters
2019 · Seunghwan Lee, Jun-Sik Yoon, et al. · Solid-State Electronics · 6
A Novel Source/Drain Extension Scheme with Laser-Spike Annealing for Nanosheet Field-Effect Transistors in 3D ICs
2023 · Sanguk Lee, Jinsu Jeong, et al. · Nanomaterials · 5
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Monolithic 3D 6T-SRAM Based on Newly Designed Gate and Source/Drain Bottom Contact Schemes
2021 · Junjong Lee, Jun-Sik Yoon, et al. · IEEE Access · 5
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Multi-Task Learning for Real-Time BSIM-CMG Parameter Extraction of NSFETs with Multiple Structural Variations
2024 · Seunghwan Lee, Seungjoon Eom, et al. · IEEE Access · 4
Comparison of impact of channel length- and width-directional taper angle in nanosheet and forksheet FETs for 2 nm node and beyond
2025 · Yonghwan Ahn, Junjong Lee, et al. · Solid-State Electronics · 3
Vertical FET Optimization at Angstrom Nodes: A Comparative Study With Horizontal FET
2025 · Junjong Lee, Jinsu Jeong, et al. · IEEE Journal of the Electron Devices Society · 2
Nonlinear Variation Decomposition of Neural Networks for Holistic Semiconductor Process Monitoring
2024 · Hyeok Yun, Hyundong Jang, et al. · Advanced Intelligent Systems · 2
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Newly Designed n-Type Stacked-Vertical FET (ST-VFET) for Area Efficient Logic Applications
2025 · Yonghwan Ahn, Junjong Lee, et al. · IEEE Journal of the Electron Devices Society · 1
Patterned Multi-Wall Nanosheet FETs for Sustainable Scaling: Zero Gate Extension With Minimal Gate Cut Width
2025 · Sanguk Lee, Jinsu Jeong, et al. · IEEE Access · 1
Works count: 40
Citation count: 268
H-index: 9
I10-index: 9
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