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Pranose J. Edavoor

Observed names: Pranose Edavoor, Pranose J Edavoor, Pranose Jose Edavoor
ORCID: 0000-0002-2133-7126
Observed ORCID: 0000-0002-2133-7126
OpenAlex ID: A5066835728
Approximate Multiplier Design Using Novel Dual-Stage 4:2 Compressors
2020 · Pranose J. Edavoor, Sithara Raveendran, et al. · IEEE Access · 144
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Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic
2021 · Sithara Raveendran, Pranose J. Edavoor, et al. · IEEE Access · 30
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An Approximate Low-Power Lifting Scheme Using Reversible Logic
2020 · Sithara Raveendran, Pranose J. Edavoor, et al. · IEEE Access · 19
A New Approach to the Design and Implementation of a Family of Multiplier Free Orthogonal Wavelet Filter Banks
2021 · Aswini K. Samantaray, Pranose J. Edavoor, et al. · IEEE Transactions on Circuits and Systems for Video Technology · 18
Power-Efficient VLSI Architecture of a New Class of Dyadic Gabor Wavelets for Medical Image Retrieval
2022 · Aswini K. Samantaray, Pranose J. Edavoor, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 15
Design and Implementation of Reversible Logic based RGB to Gray scale Color Space Converter
2018 · Sithara Raveendran, Pranose J. Edavoor, et al. · IEEE Region 10 Conference (TENCON) · 13
An efficient approach for design and testing of FPGA programming using Lab VIEW
2015 · B. Naresh Kumar Reddy, N. Suresh, et al. · International Conference on Advances in Computing, Communications and Informatics (ICACCI) · 13
Design of floating point multiplier using approximate hybrid Radix-4/ Radix-8 booth encoder for image analysis
2024 · Pranose J. Edavoor, Aswini K. Samantaray, et al. · e-Prime - Advances in Electrical Engineering Electronics and Energy · 11
Design and implementation of a novel low complexity symmetric orthogonal wavelet filter‐bank
2019 · Pranose J. Edavoor, Amol D. Rahulkar · IET Image Processing · 11
A SIMD Dynamic Fixed Point Processing Engine for DNN Accelerators
2024 · Gopal Raut, Pranose J Edavoor, et al. · International Symposium on Quality Electronic Design (ISQED) · 8
Design and Analysis of Posit Quire Processing Engine for Neural Network Applications
2023 · Pranose J Edavoor, Aneesh Raveendran, et al. · International Conference on VLSI Design · 8
A Data Flow Scheduler for Multi-precision SIMD Processing Engine Systolic Array CNN Accelerators
2024 · Ritambhara Thakur, Pranose J Edavoor, et al. · IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT) · 5
A Novel Design of Symmetric Daub-4 Wavelet Filter Bank for Image Analysis
2022 · Aswini K. Samantaray, Pranose J. Edavoor, et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 5
A Novel Design of Dyadic db3 Orthogonal Wavelet Filter Bank for Feature Extraction
2021 · Aswini K. Samantaray, Amol D. Rahulkar, et al. · Circuits Systems and Signal Processing · 5
Design and implementation of image kernels using reversible logic gates
2020 · Sithara Raveendran, Pranose Jose Edavoor, et al. · IET Image Processing · 5
Novel 4:2 Approximate Compressor Designs for Multimedia and Neural Network Applications
2020 · Pranose J. Edavoor, Sithara Raveendran, et al. · Journal of Circuits Systems and Computers · 5
A Novel Design Approach and VLSI Architecture of Rationalized Bi-Orthogonal Wavelet Filter Banks
2023 · Aswini K. Samantaray, Pranose J. Edavoor, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 4
Design and implementation of computationally efficient architecture of PID based motion controller for robotic land navigation system in FPGA
2017 · Priyanandini Das, Pranose J. Edavoor, et al. · IEEE Conference on Information and Communication Technology (CICT) · 4
Multi-Precision SIMD Posit Systolic Array Accelerator for Deep Learning
2025 · Gopal Raut, David Selvakumar, et al. · IEEE International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA) · 3
AFX-PE: Adaptive Fixed-Point Processing Engine for Neural Network Accelerators
2024 · Gopal Raut, Ritambhara Thakur, et al. · Lecture notes in electrical engineering · 2
Design and Analysis of Posit Processing Engine with Embedded Activation Functions for Neural Network Applications
2023 · Pranose J. Edavoor, Aneesh Raveendran, et al. · Lecture notes in electrical engineering · 2
On The Design Of Rationalised Bi-orthogonal Wavelet Using Reversible Logic
2022 · Sithara Raveendran, Pranose J. Edavoor, et al. · IEEE International Symposium on Circuits and Systems proceedings · 2
Reversible Logic Implementation of Image Denoising for Grayscale Images
2020 · Sithara Raveendran, Pranose J. Edavoor, et al. · IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) · 2
Implementation of adaptive image compression algorithm using varying bit-length daubechies wavelet coefficient with three-level encryption on Zynq 7000
2017 · Pranose J Edavoor, Sithara Raveendran, et al. · International Symposium on Embedded Computing and System Design (ISED) · 2
Verilog implementation of adaptive compression of RGB images at low bit rates
2015 · Arjun T V, Pranose J Edavoor, et al. · IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) · 2
Works count: 31
Citation count: 340
H-index: 9
I10-index: 9
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