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S. Ostanin

Observed names: Ostanin S.A., S Ostanin, S. A. Ostanin, S.A. Ostanin, Sergei A. Ostanin, Sergei Ostanin, Sergey A. Ostanin, Sergey Alexandrovich Ostanin, Sergey Ostanin
ORCID: 0000-0002-4204-4808
Observed ORCID: 0000-0002-4204-4808
OpenAlex ID: A5066991394
Self‐checking Synchronous FSM Network Design with Low Overhead
1999 · A. Yu. Matrosova, I. Levin, et al. · VLSI design · 63
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Self-checking synchronous FSM network design for path delay faults
2017 · S. Ostanin · IEEE East-West Design & Test Symposium (EWDTS) · 21
Survivable self-checking sequential circuits
2002 · I. Levin, A. Matrosova, et al. · Proceedings · 20
Self-checking FSM design with observing only FSM outputs
2002 · A. Matrosova, S. Ostanin · IEEE International On-Line Testing Symposium (IOLTS) · 11
Test Generation for Single and Multiple Stuck-at Faults of a Combinational Circuit Designed by Covering Shared ROBDD with CLBs
2007 · A. Matrosova, E. Loukovnikova, et al. · Proceedings · 10
A fault-tolerant sequential circuit design for soft errors based on fault-secure circuit
2016 · S. Ostanin, A. Matrosova, et al. · IEEE East-West Design & Test Symposium (EWDTS) · 8
Generating all test patterns for stuck-at faults at a gate pole and their connection with the incompletely specified Boolean function of the corresponding subcircuit
2014 · A. Matrosova, S. Ostanin, et al. · Biennial Baltic Electronics Conference (BEC) · 8
Self-checking sequential circuits with self-healing ability
2002 · Ilya Levin, Vladimir Ostrovsky, et al. · ACM Great Lakes Symposium on VLSI (GLSVLSI) · 6
Fault-tolerant high performance scheme design
2015 · A. Matrosova, S. Ostanin, et al. · IEEE East-West Design & Test Symposium (EWDTS) · 5
A fault-tolerant combinational circuit design
2015 · S. Ostanin, I. Kirienko, et al. · IEEE East-West Design & Test Symposium (EWDTS) · 5
Detection of false paths in logical circuits by joint analysis of the AND/OR trees and SSBDD-graphs
2013 · A. Yu. Matrosova, S. A. Ostanin, et al. · Automation and Remote Control · 5
Trojan circuits masking and debugging of combinational circuits with LUT insertion
2018 · A. Matrosova, S. Ostanin · IEEE International Conference on Automation, Quality and Testing, Robotics (AQTR) · 4
Patching circuit design based on reserved CLBs
2016 · A. Matrosova, S. Ostanin, et al. · IEEE International Conference on Automation, Quality and Testing, Robotics (AQTR) · 4
Increasing Manufacturing Yield Using Partially Programmable Circuits with CLB Implementation of Incompletely Specified Boolean Function of the Corresponding Sub-Circuit
2015 · A. Matrosova, S. Ostanin, et al. · IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) · 4
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Implementation by the special formula of an arbitrary subset of code words of (m, n)-code for designing a self-testing checker
2011 · N. Butorina, S. Ostanin · IEEE East-West Design & Test Symposium (EWDTS) · 4
Logic circuit design with gates, LUTs and MUXs oriented to mask faults
2017 · A. Matrosova, S. Ostanin, et al. · IEEE East-West Design & Test Symposium (EWDTS) · 3
A fault-tolerant sequential circuit design for SAFs and PDFs soft errors
2016 · A. Matrosova, S. Ostanin, et al. · IEEE International On-Line Testing Symposium (IOLTS) · 3
Partially programmable circuit design
2014 · A. Matrosova, S. Ostanin, et al. · IEEE East-West Design & Test Symposium (EWDTS) · 3
Fault latencies of concurrent checking FSMs
2003 · R. Goot, I. Levin, et al. · Euromicro Conference on Digital System Design (DSD) · 3
Masking Robust Testable PDFs
2019 · Anzhela Matrosova, Sergei Ostanin, et al. · IEEE East-West Design & Test Symposium (EWDTS) · 2
Providing Reliability of Physical Systems: Partially Programmable Circuit Design
2014 · A. Yu. Matrosova, S. A. Ostanin, et al. · Russian Physics Journal · 2
Self-healing ability of sequential circuits
2003 · I. Levin, V. Ostrovsky, et al. · IEEE Convention of Electrical and Electronics Engineers in Israel · 2
Totally Self-Checking FPGA-based FSM
2001 · Ilya Levin, V. Sinelnikov, et al. · 2
Applying SAT Solvers and ROBDDs for Deriving Circuits Masking Logical Faults and TSs in Discrete Systems
2020 · A.Yu. Matrosova, V.A. Provkin, et al. · Problems of advanced micro- and nanoelectronic systems development · 1
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Finding False Paths for Sequential Circuits Using Operations on ROBDDs
2018 · Anzhela Matrosova, Sergei Ostanin, et al. · IEEE International On-Line Testing Symposium (IOLTS) · 1
Works count: 45
Citation count: 204
H-index: 7
I10-index: 5
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