Get started
Author

Toshiki Kanamoto

Observed names: Kanamoto Toshiki, T. KANAMOTO, T. Kanamoto, Toshiki KANAMOTO, カナモト, トシキ
Institution: Hirosaki University
ORCID: 0000-0002-6326-6960
Observed ORCID: 0000-0002-6326-6960
OpenAlex ID: A5067005883
Efficient capacitance extraction method for interconnects with dummy fills
2004 · A. Kurokawa, T. Kanamoto, et al. · IEEE Custom Integrated Circuits Conference (CICC) · 41
Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills
2005 · A. Kurokawa, T. Kanamoto, et al. · International Symposium on Quality of Electronic Design (ISQED) · 35
Thermal Model and Countermeasures for Future Smart Glasses
2020 · Kodai Matsuhashi, Toshiki Kanamoto, et al. · Sensors · 28
PDF
Neural Network-Based 3D IC Interconnect Capacitance Extraction
2019 · Ryosuke Kasai, Toshiki Kanamoto, et al. · International Conference on Communication Engineering and Technology (ICCET) · 19
Thermal placement on PCB of components including 3D ICs
2020 · Yuuta Satomi, Koutaro Hachiya, et al. · IEICE Electronics Express · 18
PDF
Supply Noise Suppression by Triple-Well Structure
2012 · Yasuhiro Ogasahara, Masanori Hashimoto, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 15
Interconnect Modeling: A Physical Design Perspective
2009 · Atsushi Kurokawa, Takashi Sato, et al. · IEEE Transactions on Electron Devices · 15
Measurement of supply noise suppression by substrate and deep N-well in 90nm process
2008 · Yasuhiro Ogasahara, Masanori Hashimoto, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 15
Test structure measuring inter- and intralayer coupling capacitance of interconnection with subfemtofarad resolution
2004 · T. Kunikiyo, T. Watanabe, et al. · IEEE Transactions on Electron Devices · 15
Impact of well edge proximity effect on timing
2007 · Toshiki Kanamoto, Yasuhiro Ogasahara, et al. · Proceedings of ESSCIRC · 13
A Single-Stage RISC-V Processor to Mitigate the Von Neumann Bottleneck
2019 · Toshiki Kanamoto, Masami Fukushima, et al. · Conference proceedings · 12
Hardware Trojan Insertion and Detection in Asynchronous Circuits
2019 · Koutaro Inaba, Tomohiro Yoneda, et al. · Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems · 12
The D30V/MPEG multimedia processor
1999 · H. Takata, T. Watanabe, et al. · IEEE Micro · 12
Bayesian neural network based inductance calculations of wireless power transfer systems
2023 · Kai Sato, Toshiki Kanamoto, et al. · IEICE Electronics Express · 8
PDF
A VOHE System for Underwater Communications
2020 · Yang Peng, Tomoyuki Nagase, et al. · Electronics · 7
PDF
A Multicore Chip Load Model for PDN Analysis Considering Voltage–Current-Timing Interdependency and Operation Mode Transitions
2019 · Jun Chen, Hajime Kando, et al. · IEEE Transactions on Components Packaging and Manufacturing Technology · 7
A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures
2005 · T. KANAMOTO · IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences · 7
Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF
2003 · Takashi Sato, Toshiki Kanamoto, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 6
A Virtual Optical Holographic Encryption System Using Expanded Diffie-Hellman Algorithm
2021 · Yang Peng, Tomoyuki Nagase, et al. · IEEE Access · 5
PDF
Optimization of Full-Chip Power Distribution Networks in 3D ICs
2018 · Yuuta Satomi, Koutaro Hachiya, et al. · IEEE International Conference on Integrated Circuits and Microsystems (ICICM) · 5
Compensation capacitance tunings of wireless power transfer systems using artificial neural network
2024 · Kai Sato, Koutaro Hachiya, et al. · IEICE Communications Express · 4
PDF
Deep Neural Network Based Inductance Calculations of Wireless Power Transfer Systems
2022 · Kai Sato, Toshiki Kanamoto, et al. · IEEE Global Conference on Consumer Electronics (GCCE) · 4
Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF
2003 · T. Sato, T. Kanamoto, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 4
Impact of Well Edge Proximity Effect on Timing
2008 · T. KANAMOTO, Y. OGASAHARA, et al. · IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences · 3
Non-destructive inverse modeling of copper interconnect structure for 90nm technology node
2003 · T. Kunikiyo, T. Watanabe, et al. · International Conference on Simulation of Semiconductor Processes and Devices · 3
Works count: 68
Citation count: 350
H-index: 12
I10-index: 13
Year
Topic
Type