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Puneet Sareen

Observed name: P. Sareen
OpenAlex ID: A5067257171
A new low power and area efficient semi-digital PLL architecture for low bandwidth applications
2011 · Markus Dietl, Puneet Sareen · ACM Great Lakes Symposium on VLSI (GLSVLSI) · 5
Low power, small die-size PLL using semi-digital storage instead of big loop filter capacitance
2010 · Markus Dietl, Puneet Sareen · Networked Embedded Systems for Enterprise Applications · 5
A −245 dB FOM 48 fs rms jitter semi-digital PLL with intrinsic temperature compensation in 130 nm CMOS
2017 · J. Anders, S. Bader, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 4
Very high bandwidth semi-digital PLL with large operating frequency range
2011 · Vivek Elangovan, Markus Dietl, et al. · NORCHIP · 4
A low power, self-biased, bandwidth tracking semi-digital PLL design
2012 · Mitesh Yogesh, Markus Dietl, et al. · IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA) · 2
Inductor Mismatch Compensation in Parallel Operation Multi-Phase DC-DC Converters Using Ripple-Based Self-Balancing Control
2025 · Narayanan Seetharaman, Puneet Sareen · Global Power, Energy and Communication Conference · 1
A 2.5 GHz self-compensated, bandwidth tracking PLL with 0.8 ps jitter
2012 · Mitesh Yogesh, Puneet Sareen, et al. · NORCHIP · 1
Low power and area efficient semi-digital PLL for low bandwidth applications
2011 · Markus Dietl, Puneet Sareen · International Symposium on VLSI Design, Automation and Test · 1
A Low Power and Small Die-Size Phase-Locked Loop Circuit Using Semi-Digital Storage
2011 · Markus Dietl, Puneet Sareen · 1
Multi-Phase, Multi-chip DCDC Converter Control Architecture for High Power Applications
2026 · Puneet Sareen, Narayanan Seetharaman · Global Power, Energy and Communication Conference
Ring VCO based ultra low jitter PLL architecture.
2018 · T. Khan, M. Dietl, et al. · International Conference on Solid State Devices and Materials (SSDM)
A BW-tracking semi-digital PLL with near-optimal VCO phase noise shaping in low-cost 0.4 µm CMOS achieving 700 fs rms phase jitter
2015 · S. Fahmy, M. Dietl, et al. · IEEE Nordic Circuits and Systems Conference (NorCAS)
A novel approach of cap-sharing to reduce the big loop filter capacitance in semi-digital PLL
2011 · Ketan Dewan, Puneet Sareen, et al. · International Semiconductor Device Research Symposium
Cap-sharing technique to reduce on chip capacitance in semi-digital phase lock loops
2011 · Puneet Sareen, Ketan Dewan, et al. · IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)
A novel approach of Cap-sharing to reduce the big loop filter capacitance in semi-digital PLL
2011 · K. Dewan, P. Sareen, et al. · International Conference on Solid State Devices and Materials (SSDM)
Works count: 16
Citation count: 24
H-index: 4
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