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Yvain Thonnart

IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management
2020 · Pascal Vivet, Eric Guthmuller, et al. · IEEE Journal of Solid-State Circuits · 134
An Asynchronous Power Aware and Adaptive NoC Based Circuit
2009 · Edith Beigne, Fabien Clermidy, et al. · IEEE Journal of Solid-State Circuits · 99
A 477mW NoC-based digital baseband for MIMO 4G SDR
2010 · Fabien Clermidy, Christian Bernard, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 90
A fully-asynchronous low-power framework for GALS NoC integration
2010 · Y Thonnart, P Vivet, et al. · Design, Automation, and Test in Europe · 83
A fully-asynchronous low-power framework for GALS NoC integration
2010 · Yvain Thonnart, Pascal Vivet, et al. · Design, Automation, and Test in Europe · 76
19.2 A 110mK 295µW 28nm FDSOI CMOS Quantum Integrated Circuit with a 2.8GHz Excitation and nA Current Sensing of an On-Chip Double Quantum Dot
2020 · Loick Le Guevel, Gerard Billiot, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 75
2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters
2020 · Pascal Vivet, Eric Guthmuller, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 62
Optimizing Resource Efficiencies for Scalable Full-Stack Quantum Computers
2023 · Marco Fellous-Asiani, Jing Hao Chai, et al. · PRX Quantum · 57
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Silicon photonics for terabit/s communication in data centers and exascale computers
2020 · S. Bernabé, Q. Wilmart, et al. · Solid-State Electronics · 55
Design and Implementation of a GALS Adapter for ANoC Based Architectures
2009 · Yvain Thonnart, Edith Beigné, et al. · IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) · 54
A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking
2014 · Edith Beigne, Alexandre Valentian, et al. · IEEE Journal of Solid-State Circuits · 49
A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking
2014 · Robin Wilson, Edith Beigne, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 46
A 0.9 pJ/bit, 12.8 GByte/s WideIO memory interface in a 3D-IC NoC-based MPSoC
2013 · Denis Dutoit, Christian Bernard, et al. · Symposium on VLSI Circuits · 44
An Open and Reconfigurable Platform for 4G Telecommunication: Concepts and Application
2009 · Fabien Clermidy, Romain Lemaire, et al. · Euromicro Conference on Digital System Design (DSD) · 44
Efficiency Optimization of Silicon Photonic Links in 65-nm CMOS and 28-nm FDSOI Technology Nodes
2016 · Robert Polster, Yvain Thonnart, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 39
A Pseudo-Synchronous Implementation Flow for WCHB QDI Asynchronous Circuits
2012 · Yvain Thonnart, Edith Beigne, et al. · IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) · 38
A $4 \times 4 \times 2$ Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links
2016 · Pascal Vivet, Yvain Thonnart, et al. · IEEE Journal of Solid-State Circuits · 37
An analytical method for evaluating Network-on-Chip performance
2010 · Sahar Foroutan, Yvain Thonnart, et al. · Design, Automation, and Test in Europe · 37
POPSTAR: a Robust Modular Optical NoC Architecture for Chiplet-based 3D Integrated Systems
2020 · Yvain Thonnart, Stephane Bernabe, et al. · Design, Automation, and Test in Europe · 36
Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip
2007 · Gwen Salaun, Wendelin Serwe, et al. · IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) · 33
Coherent and Incoherent Crosstalk Noise Analyses in Interchip/Intrachip Optical Interconnection Networks
2016 · Luan H. K. Duong, Zhehui Wang, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 27
An asynchronous power aware and adaptive NoC based circuit
2008 · E. Beigne, F. Clermidy, et al. · Symposium on VLSI Circuits · 27
SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration
2022 · Ivan Miro-Panades, Benoit Tain, et al. · IEEE Journal of Solid-State Circuits · 26
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A Fine-Grain Variation-Aware Dynamic ${\rm Vdd}$ -Hopping AVFS Architecture on a 32 nm GALS MPSoC
2014 · Ivan Miro-Panades, Edith Beigne, et al. · IEEE Journal of Solid-State Circuits · 25
An Iterative Computational Technique for Performance Evaluation of Networks-on-Chip
2012 · Sahar Foroutan, Yvain Thonnart, et al. · IEEE Transactions on Computers · 25
Works count: 105
Citation count: 1,948
H-index: 25
I10-index: 52
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