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D.C.H. Yu
Observed names:
D. C. H. Yu,
D. C. Yu,
D. Yu,
D.C. Yu,
Dayang Yu
Institutions:
Beijing Technology and Business University,
Wuhan University
Observed institutions:
AT&T (United States),
Beijing Technology and Business University,
Wuhan University,
Taiwan Semiconductor Manufacturing Company (Taiwan)
ORCID:
0000-0002-4251-9607
Observed ORCID:
0000-0002-4251-9607
OpenAlex ID:
A5068583042
Characterization and modeling of edge direct tunneling (EDT) leakage in ultrathin gate oxide MOSFETs
2001
·
K.N. Yang
, H.T. Huang
, et al.
·
IEEE Transactions on Electron Devices
·
54
Low-k dielectrics characterization for damascene integration
2001
·
S. Lin
, Changming Jin
, et al.
·
IEEE International Interconnect Technology Conference (IITC)
·
26
Correlation between Processing, Composition, and Mechanical Properties of PECVD-SiN, Thin Films
1990
·
D. C. H. Yu
, J. A. Taylor
·
MRS Proceedings
·
10
Regulating the Electronegativity Difference and Piezoelectric Strain of the S–Mo–S Structure via Introducing Mo Vacancies for Boosting Piezo-Photoelectric Activity
2025
·
Yuting Ning
, Xinping Fu
, et al.
·
ACS Applied Materials & Interfaces
·
9
A novel switchable BARC (SBARC) and process to improve pattern collapse and defect control
2006
·
Ching Yu Chang
, D. C. Yu
, et al.
·
Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE
·
6
Step coverage study of PETEOS deposition for intermetal dielectric applications
2002
·
D. Yu
, D. Favreau
, et al.
·
International IEEE VLSI Multilevel Interconnection Conference
·
5
Edge hole direct tunneling leakage in ultrathin gate oxide p-channel MOSFETs
2001
·
Kuo-Nan Yang
, Huan-Tsung Huang
, et al.
·
IEEE Transactions on Electron Devices
·
4
Low threshold voltage CMOS devices with smooth topography for 1 volt applications
2002
·
D.C.H. Yu
, H.D. Lin
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
3
CMP-free and CMP-less approaches for multilevel Cu/low-k BEOL integration
2002
·
M.H. Tsai
, S.W. Chou
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
3
Improving CMOS speed at low supply voltages
2002
·
Horng-Dar Lin
, Ran-Hong Yan
, et al.
·
IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD)
·
2
Development of cleaning process for immersion lithography
2006
·
Ching Yu Chang
, D.C. Yu
, et al.
·
Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE
·
1
To optimize electrical properties of the ultrathin (1.6 nm) nitride/oxide gate stacks with bottom oxide materials and post-deposition treatment
2001
·
Chein-Hao Chen
, Yean-Kuen Fang
, et al.
·
IEEE Transactions on Electron Devices
·
1
Research of In0.48Ga0.52P/GaAs Heterojunction Interface Properties Improvement Deposited by MOCVD
2025
·
Dayang Yu
, Junjie Qiu
, et al.
·
Crystal Research and Technology
Robust n/sup +//p/sup +/ dual-gate cmos device fabrication using dopant drive-out technique
2005
·
D.C.H. Yu
, K.H. Lee
, et al.
·
International Electron Devices and Materials Symposium
Improvement of window profile and metal step coverage for submicron CMOS devices
2002
·
D.C.H. Yu
, K.H. Lee
·
International IEEE VLSI Multilevel Interconnection Conference
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Works count:
15
Citation count:
124
H-index:
5
I10-index:
3
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