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Andy Gean Ye

Observed names: Andy Ye, Ye Andy
ORCID: 0000-0002-2959-5736
Observed ORCID: 0000-0002-2959-5736
OpenAlex ID: A5068830776
VPR 5.0
2009 · Jason Luu, Ian Kuon, et al. · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) · 198
VPR 5.0
2011 · Jason Luu, Ian Kuon, et al. · ACM Transactions on Reconfigurable Technology and Systems · 71
Design techniques for decision feedback equalisation of multi‐giga‐bit‐per‐second serial data links: a state‐of‐the‐art review
2014 · Fei Yuan, Alaa R. AL‐Taee, et al. · IET Circuits Devices & Systems · 24
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Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits
2005 · Andy Ye, Jonathan Rose · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) · 23
An Evaluation on the Accuracy of the Minimum-Width Transistor Area Models in Ranking the Layout Area of FPGA Architectures
2018 · Farheen Fatima Khan, Andy Ye · ACM Transactions on Reconfigurable Technology and Systems · 16
Measuring the Accuracy of Minimum Width Transistor Area in Estimating FPGA Layout Area
2015 · Farheen Fatima Khan, Andy Ye · IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) · 15
An evaluation on the accuracy of the minimum width transistor area models in ranking the layout area of FPGA architectures
2016 · Farheen Fatima Khan, Andy Ye · International Conference on Field Programmable Logic and Applications (FPL) · 14
New 2-D Eye-Opening Monitor for Gb/s Serial Links
2013 · Alaa R. AL-Taee, Fei Yuan, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 14
The Effect of Multi-Bit Correlation on the Design of Field-Programmable Gate Array Routing Resources
2009 · Phoebe Ping Chen, Andy Ye · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 14
Field-programmable gate array architectures and algorithms optimized for implementing datapath circuits
2004 · Jonathan Rose, David Lewis, et al. · 12
A study on the accuracy of minimum width transistor area in estimating FPGA layout area
2017 · Farheen Fatima Khan, Andy Ye · Microprocessors and Microsystems · 9
Using the Minimum Set of Input Combinations to Minimize the Area of Local Routing Networks in Logic Clusters Containing Logically Equivalent I/Os in FPGAs
2009 · Andy Gean Ye · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 9
Designing efficient FPGA tiles for power-constrained ultra-low-power applications
2021 · Anas Razzaq, Sajjad Rostami Sani, et al. · Integration · 8
Measuring the Accuracy of Layout Area Estimation Models of Tile-Based FPGAs in FinFET Technology
2020 · Sajjad Rostami Sani, Farheen Fatima Khan, et al. · International Conference on Field Programmable Logic and Applications (FPL) · 7
A scalable computing and memory architecture for variable block size motion estimation on Field-Programmable Gate Arrays
2008 · Theepan Moorthy, Andy Ye · International Conference on Field Programmable Logic and Applications (FPL) · 7
Analysis and architecture design of scalable fractional motion estimation for H.264 encoding
2011 · Jasmina Vasiljevic, Andy Ye · Integration · 6
Static power model for CMOS and FPGA circuits
2021 · Anas Razzaq, Andy Ye · IET Computers & Digital Techniques · 5
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Two-dimensional eye-opening monitor for serial links
2013 · Alaa R. AL-Taee, Fei Yuan, et al. · Conference proceedings · 5
Audio scene analysis using parametric signal features
2011 · Hamid Asefi, Behnaz Ghoraani, et al. · Conference proceedings - Canadian Conference on Electrical and Computer Engineering · 5
An improved RC model for VLSI interconnects with applications to buffer insertion
2013 · Alaa R. Al-Taee, Fei Yuan, et al. · Analog Integrated Circuits and Signal Processing · 4
A scalable architecture for variable block size motion estimation on Field-Programmable Gate Arrays
2008 · Theepan Moorthy, Andy Ye · Conference proceedings - Canadian Conference on Electrical and Computer Engineering · 4
Evaluating the Impact of Using Multiple-Metal Layers on the Layout Area of Switch Blocks for Tile-Based FPGAs in FinFET 7nm
2024 · Sajjad Rostami Sani, Andy Ye · ACM Transactions on Reconfigurable Technology and Systems · 3
Measuring the effect of track count and wire segment length on the layout area of switch blocks for tile-based FPGAs
2022 · Sajjad Rostami-Sani, Andy Ye · Microprocessors and Microsystems · 3
Adaptive Decision Feedback Equalizer with Hexagon EOM and Jitter Detection
2015 · Alaa R. Al-Taee, Fei Yuan, et al. · Circuits Systems and Signal Processing · 3
A new adaptive Decision Feedback Equalizer using hexagon eye-opening monitor for multi Gbps data links
2014 · Alaa R. AL-Taee, Fei Yuan, et al. · IEEE International Symposium on Circuits and Systems proceedings · 3
Works count: 54
Citation count: 509
H-index: 10
I10-index: 10
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