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Gerrit W. den Besten

Observed names: G. W. den Besten, G.W. den Besten
Institution: NXP (Netherlands)
OpenAlex ID: A5069433605
Embedded 5 V-to-3.3 V voltage regulator for supplying digital IC's in 3.3 V CMOS technology
1998 · G.W. den Besten, B. Nauta · IEEE Journal of Solid-State Circuits · 96
A 0.2–2 Gb/s 6x OSR Receiver Using a Digitally Self-Adaptive Equalizer
2008 · Friedel Gerfers, Gerrit W. den Besten, et al. · IEEE Journal of Solid-State Circuits · 34
30.1 Single-Pair Automotive PHY Solutions from 10Mb/s to 10Gb/s and Beyond
2019 · Gerrit W. den Besten · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 14
Embedded 5V-to-3.3V voltage regulator for supplying digital ICs in 3.3V CMOS technology
1997 · Gerrit W. den Besten, Bram Nauta · European Solid-State Circuits Conference (ESSCIRC) · 10
A 1.2–6 Gb/s, 4.2 pJ/Bit Clock & Data Recovery Circuit With High Jitter Tolerance in 0.14 $\mu$ m CMOS
2012 · Arnoud P. van der Wel, Gerrit W. den Besten · IEEE Journal of Solid-State Circuits · 7
Embedded low-cost 1.2 Gb/s inter-IC serial data link in 0.35 μm CMOS
2002 · G.W. den Besten · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 7
A Robust High Speed Serial PHY Architecture With Feed-Forward Correction Clock and Data Recovery
2009 · William Redman-White, Martin Bugbee, et al. · IEEE Journal of Solid-State Circuits · 5
Linear CMOS V-I Conversion Structure with Tunable Transconductance
1994 · Gerrit W. den Besten, R.F. Wassenaar, et al. · 3
Current-steering pre-emphasis transmitter with continuously tuned line terminations for optimum impedance match and maximum signal drive range
2013 · Gerrit W. den Besten, Harold G. Hanson, et al. · Custom Integrated Circuits Conference · 1
A 1.2–6 Gb/s, 4.2 pJ/bit Clock & Data Recovery circuit with high jitter tolerance in 0.14μm CMOS
2011 · A. P. van der Wel, G. W. den Besten · European Solid-State Circuits Conference (ESSCIRC) · 1
The USB 2.0 Physical Layer: Standard and Implementation
2003 · Gerrit W. den Besten · Springer eBooks · 1
Session 23 overview: Short-reach links, XCVR techniques, & PLLs
2013 · Gerrit W. den Besten, Koichi Yamaguchi · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
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A robust 1.5Gb/s + 3Gb/s serial PHY with feed-forward correction clock and data recovery
2008 · W. Redman-White, M. Bugbee, et al. · European Solid-State Circuits Conference (ESSCIRC)
High-Speed Serial Wired Interface for Mobile Applications
2008 · Gerrit W. den Besten · Springer eBooks
Data Link in 0.35∝m CMOS
2000 · Gerrit W. den Besten
Works count: 15
Citation count: 179
H-index: 6
I10-index: 4
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