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Jayashree C. Nidagundi

Observed name: Jayashree C Nidagundi
ORCID: 0000-0001-8910-5826
Observed ORCID: 0000-0001-8910-5826
OpenAlex ID: A5069989445
Design of fast and efficient 1-bit full adder and its performance analysis
2014 · Kunjan D. Shinde, Jayashree C. Nidagundi · International Conference on Control, Instrumentation, Communication and Computational Technologies · 13
Flexible hardware architecture for LDPC encoder
2016 · Jayashree C. Nidagundi, Siddarama R. Patil · Online International Conference on Green Engineering and Technologies · 5
Design and Implementation of Low Power Phase Frequency Detector (PFD) for PLL
2013 · Jayashree C. Nidagundi, Harish Desai, et al. · 2
Industry Linked Projects as Tools for Improving Employability of Budding Engineers
2023 · Siddalingesh S. Navalgund, Jayashree C. Nidagundi, et al. · Journal of Engineering Education/Journal of engineering education transformations/Journal of engineering education transformation · 1
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Design of I/O Interface for DDR2 SDRAM Transmitter Using gpdk 180 nm Technology
2021 · Jayashree C. Nidagundi · Communications in computer and information science · 1
Privacy-preserving Blockchain-enabled Federated Learning with Hierarchical Clustering for Electronic Health Records
2026 · Shweta Madiwalar, Jayashree C Nidagundi · International journal of intelligent engineering and systems
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Beyond sight: ML techniques for image classification
2025 · Jayashree C. Nidagundi, Muskansaba M. Shahiwale, et al. · CRC Press eBooks
Iot Enabled Health Monitoring System
2023 · Jayashree C Nidagundi · Iterative International Publishers eBooks
Design of Time Efficient 8-Bit Ring Counter using Pulsed Latches
2021 · Vanishri Yandigeri, Jayashree C. Nidagundi
Efficient Design of Lvds Transmitter in Compliance With Ieee Standard 1596.3-1996
2020 · Jayashree C Nidagundi · ICTACT Journal on Microelectronics
FPGA Implementation of a 32-Bit MIPS Processor
2019 · Vishala A. Tyamanavar, Jayashree C. Nidagundi
Comparative Analysis of 8-bit Adders for Embedded Application
2018 · Kunjan D. Shinde, Jayashree C. Nidagundi
High throughput structured LDPC layered decoder
2017 · Jayashree C. Nidagundi, Siddarama R. Patil · International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET)
Performance Comparison of Binary LDPC Decoders and FPGA Implementation of Encoder
2016 · Jayashree C. Nidagundi, Dr. Siddarama R. Patil · Bonfring International Journal of Research in Communication Engineering
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FPGA Implementation of Fast Error Correction and Detection for Memories
2013 · Kunjan D. Shinde, Jayashree C. Nidagundi
Low Power and High Speed Clock Triggered Comparator using 0.18μm Technology
2011 · M. Naveenkumar, N.P. Suchithra, et al. · CiiT international journal of programmable device circuits and systems
Hardware Implementation of CRC Architectures
2010 · Jayashree C. Nidagundi, Renuka H. Korti · CiiT international journal of programmable device circuits and systems
Works count: 18
Citation count: 22
H-index: 2
I10-index: 1
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