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T. Nirmalraj

Observed names: Nirmalraj T, Nirmalraj T., Nirmalraj Thirugnanasambandam, T. NIRMALRAJ, T.Nirmalraj
Institution: SASTRA University
Observed institution: SASTRA University
ORCID: 0000-0001-5293-4452
Observed ORCID: 0000-0001-5293-4452
OpenAlex ID: A5070069583
Design of Low-Power 10-Transistor Full Adder Using GDI Technique for Energy-Efficient Arithmetic Applications
2023 · T. Nirmalraj, S. K. Pandiyan, et al. · Circuits Systems and Signal Processing · 12
An enhanced Gate Diffusion Input technique for low power applications
2019 · S. Radhakrishnan, T. Nirmalraj, et al. · Microelectronics Journal · 8
Fault Tolerant Carry Save Adders - A NMR Configuration Approach
2018 · S. Radhakrishnan, T. Nirmalraj, et al. · International Conference on Control, Power, Communication and Computing Technologies (ICCPCCT) · 8
Automatic diagnosis of single fault in interconnect testing of SRAM‐based FPGA
2021 · T. Nirmalraj, S. Radhakrishnan, et al. · IET Computers & Digital Techniques · 5
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An Efficient Design for Area-Efficient Truncated Adaptive Booth Multiplier for Signal Processing Applications
2020 · S. Radhakrishnan, Rakesh Kumar Karn, et al. · Journal of Circuits Systems and Computers · 5
Design of Low Power and High Speed MAC based FIR Filter using Hybrid Adder and Modified Booth Multiplier
2020 · S. Radhakrishnan, Rakesh Kumar Karn, et al. · IEEE International Conference on Emerging Electronics (ICEE) · 4
Development of single channel EEG Acquisition system for BCI applications
2021 · V.G. Rajendran, Jayalalitha S., et al. · Research Journal of Pharmacy and Technology · 2
Low latency power aware selfchecking based CSA for sequential multiplier
2017 · S. Radhakrishnan, T. Nirmalraj, et al. · IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI) · 2
Design of low power, high speed PLL frequency synthesizer using dynamic CMOS VLSI technology
2017 · T. Nirmalraj, S. Radhakrishnan, et al. · IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI) · 1
Design and Implementation of a Low-Cost, Low-Power FPGA and RFID-Based Remote Vehicle Speed Detection System
2026 · Mohamed Agha Sardjanto, Nirmalraj Thirugnanasambandam, et al. · International Journal of RF Technologies
Quantum-Inspired Cheetah Optimization Algorithm for Energy-Efficient Cluster Head Selection in Wireless Sensor Networks
2026 · Thalaimalaichamy M, Nirmalraj T, et al. · International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET)
New Age Cryptanalysis: Side Channel Attack (SCA) – Investigation of Differential Power Attack on AES-128 Architecture
2025 · Sivaraman R, Mokina Siva Satya Krishna, et al. · International Conference on Power, Instrumentation, Control and Computing (PICC)
Code Multiplexed VLSI Test Architecture for SOC Testing
2023 · Meerasha, Mubarak Ali, S.Radhakrishnan, et al. · Zenodo (CERN European Organization for Nuclear Research)
A survey on generating a strong password
2021 · T. Nirmalraj, J.Jebathagam · Annals of the Romanian Society for Cell Biology
Enhanced Self Checking Carry Select Adder using Dynamic Logic Based Full Adder
2020 · S. Radhakrishnan*, Rakesh Kumar Karn, et al. · International Journal of Recent Technology and Engineering (IJRTE)
Low Power and Improved Speed 1t Dram Using Dynamic Logic
2018 · T. NIRMALRAJ, S. K. PANDIYAN, et al. · Siti Hasmah Digital Library-MMU Institutiona Repository (Multimedia University)
Natural Tragedy Commendation Hasty Alert Using Tweet Events Over Distributed Processing Framework
2016 · R. Pushpanathan, T. Nirmalraj, et al. · International Journal of Advanced Engineering Research and Science
Low Power Dual Stack in Mtcmos Circuits Using Dynamic Logic and Sleep Transistor Techniques
2016 · T. Nirmalraj, S. K. Pandiyan, et al. · Far East Journal of Electronics and Communications
Works count: 18
Citation count: 47
H-index: 5
I10-index: 1
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