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Hemangee K. Kapoor

Observed names: H. K. Kapoor, H. Kapoor, H.K. Kapoor, HEMANGEE K. KAPOOR, Hemangee K Kapoor, Hemangee Kalpesh Kapoor, Hemangee Kapoor, K Kapoor Hemangee, Kapoor, Hemangee K
ORCID: 0000-0002-9376-7686
Observed ORCID: 0000-0002-9376-7686
OpenAlex ID: A5070605948
A Security Framework for NoC Using Authenticated Encryption and Session Keys
2013 · Hemangee K. Kapoor, G. Bhoopal Rao, et al. · Circuits Systems and Signal Processing · 48
An Authenticated Encryption Based Security Framework for NoC Architectures
2011 · K. Sajeesh, Hemangee K. Kapoor · International Symposium on Electronic System Design · 33
Cost effective routing techniques in 2D mesh NoC using on-chip transmission lines
2018 · Dipika Deb, John Jose, et al. · Journal of Parallel and Distributed Computing · 30
Improving the Lifetime of Non-Volatile Cache by Write Restriction
2019 · Sukarn Agarwal, Hemangee K. Kapoor · IEEE Transactions on Computers · 23
Analysing the Role of Last Level Caches in Controlling Chip Temperature
2018 · Shounak Chakraborty, Hemangee K. Kapoor · IEEE Transactions on Sustainable Computing · 19
Energy aware frame based fair scheduling
2018 · Sanjay Moulik, Arnab Sarkar, et al. · Sustainable Computing Informatics and Systems · 19
TARTS: A Temperature-Aware Real-Time Deadline-Partitioned Fair Scheduler
2020 · Sanjay Moulik, Arnab Sarkar, et al. · Journal of Systems Architecture · 18
Modelling and verification of delay-insensitive circuits using CCS and the Concurrency Workbench
2004 · Hemangee K. Kapoor, Mark B. Josephs · Information Processing Letters · 17
Reuse-Distance-Aware Write-Intensity Prediction of Dataless Entries for Energy-Efficient Hybrid Caches
2018 · Sukarn Agarwal, Hemangee K. Kapoor · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 16
DPFair Scheduling with Slowdown and Suspension
2018 · Sanjay Moulik, Arnab Sarkar, et al. · International Conference on VLSI Design · 16
Victim retention for reducing cache misses in tiled chip multiprocessors
2013 · Shirshendu Das, Hemangee K. Kapoor · Microprocessors and Microsystems · 15
Fault Tolerance in Network on Chip Using Bypass Path Establishing Packets
2018 · Sharma Priya, Sukarn Agarwal, et al. · International Conference on VLSI Design · 14
Restricting writes for energy-efficient hybrid cache in multi-core architectures
2016 · Sukarn Agarwal, Hemangee K. Kapoor · IFIP/IEEE International Conference on Very Large Scale Integration · 13
nZESPA: A Near-3D-Memory Zero Skipping Parallel Accelerator for CNNs
2020 · Palash Das, Hemangee K. Kapoor · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 12
WELCOMF
2020 · Arijit Nath, Hemangee K. Kapoor · International Symposium on Low Power Electronics and Design (ISLPED) · 12
Formal Approach for DVS-Based Power Management for Multiple Server System in Presence of Server Failure and Repair
2012 · Lalit Chandnani, Hemangee K. Kapoor · IEEE Transactions on Industrial Informatics · 12
Dynamic reconfiguration of embedded-DRAM caches employing zero data detection based refresh optimisation
2019 · Sheel Sindhu Manohar, Hemangee K. Kapoor · Journal of Systems Architecture · 11
Towards a Better Lifetime for Non-volatile Caches in Chip Multiprocessors
2017 · Sukarn Agarwal, Hemangee K. Kapoor · International Conference on VLSI Design · 11
Exploration of Migration and Replacement Policies for Dynamic NUCA over Tiled CMPs
2015 · Shirshendu Das, Hemangee K. Kapoor · International Conference on VLSI Design · 11
Dynamic Associativity Management Using Fellow Sets
2013 · Shirshendu Das, Hemangee K. Kapoor · International Symposium on Electronic System Design · 11
Exploring the Role of Large Centralised Caches in Thermal Efficient Chip Design
2019 · Shounak Chakraborty, Hemangee K. Kapoor · ACM Transactions on Design Automation of Electronic Systems · 10
Targeting inter set write variation to improve the lifetime of non-volatile cache using fellow sets
2017 · Sukarn Agarwal, Hemangee K. Kapoor · IFIP/IEEE International Conference on Very Large Scale Integration · 10
Static energy reduction by performance linked cache capacity management in tiled CMPs
2015 · Hemangee K. Kapoor, Shirshendu Das, et al. · ACM Symposium on Applied Computing · 10
CAPMIG: Coherence-Aware Block Placement and Migration in Multiretention STT-RAM Caches
2022 · Sheel Sindhu Manohar, Hemangee K. Kapoor · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 9
Towards a Better Cache Utilization Using Controlled Cache Partitioning
2013 · Prateek D. Halwe, Shirshendu Das, et al. · IEEE Intl Conf on Dependable, Autonomic and Secure Computing, Intl Conf on Pervasive Intelligence and Computing, Intl Conf on Cloud and Big Data Computing, Intl Conf on Cyber Science and Technology Congress (DASC/PiCom/CBDCom/CyberSciTech) · 9
Works count: 153
Citation count: 711
H-index: 13
I10-index: 23
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