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Author

Ye Chi

Observed name: Chi, Ye
ORCID: 0000-0001-5222-3562
Observed ORCID: 0000-0001-5222-3562
OpenAlex ID: A5071337044
A Hybrid Memory Architecture Supporting Fine-Grained Data Migration
2022 · Ye Chi, Jianhui Yue, et al. · Frontiers of Computer Science · 9
A novel parallel deblocking filtering strategy for HEVC/H.265 based on GPU
2016 · Wenbin Jiang, Hongyan Mei, et al. · Concurrency and Computation Practice and Experience · 8
A Novel GPU-Based Efficient Approach for Convolutional Neural Networks with Small Filters
2016 · Wenbin Jiang, Yiming Chen, et al. · Journal of Signal Processing Systems · 7
A Novel Fast Approach for Convolutional Networks with Small Filters Based on GPU
2015 · Wenbin Jiang, Yiming Chen, et al. · 4
A Fine-Grained Parallel Intra Prediction for HEVC Based on GPU
2016 · Wenbin Jiang, Ye Chi, et al. · IEEE International Conference on Parallel and Distributed Systems (ICPADS) · 3
Transformer: An OS-Supported Reconfigurable Hybrid Memory Architecture
2022 · Ye Chi, Haikun Liu, et al. · Applied Sciences · 2
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FIPIP: A novel fine-grained parallel partition based intra-frame prediction on heterogeneous many-core systems
2016 · Wenbin Jiang, Min Long, et al. · Future Generation Computer Systems · 2
A New Approach for Vehicle Recognition and Tracking in Multi-camera Traffic System
2015 · Wenbin Jiang, Zhiwei Lu, et al. · Lecture notes in computer science · 1
WinDlp
2026 · Feiping Wang, Ye Chi, et al. · International Journal of Information System Modeling and Design
Windlp: A High-Performance Programmable Data Leakage Prevention System Based on Kernel-Level Monitoring for Windows Platforms
2025 · Chengjian Liu, Feiping Wang, et al. · SSRN Electronic Journal
P3DC: Reducing DRAM Cache Hit Latency by Hybrid Mappings
2024 · Ye Chi, Ren-Tong Guo, et al. · Journal of Computer Science and Technology
Gemini: Reducing DRAM Cache Hit Latency by Hybrid Mappings
2018 · Chi, Ye · arXiv (Cornell University)
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Works count: 12
Citation count: 36
H-index: 4
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