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Krzysztof Koźmiński
Observed names:
K. Kozminski,
K.A. Kozminski,
Krzysztof Kozminski,
Krzysztof Kozminski
Institution:
MCNC Research and Development Institute
Observed institutions:
Warsaw University of Technology,
University of Ljubljana,
Duke University,
MCNC Research and Development Institute,
University of Rochester
OpenAlex ID:
A5073020485
Combinational profiles of sequential benchmark circuits
2003
·
F. Brglez
, D. Bryan
, et al.
·
IEEE International Symposium on Circuits and Systems proceedings
·
2,047
Rectangular duals of planar graphs
1985
·
Krzysztof Koźmiński
, Edwin Kinnen
·
Networks
·
167
An Algorithm for Finding a Rectangular Dual of a Planar Graph for Use in Area Planning for VLSI Integrated Circuits
1984
·
K. Kozminski
, E. Kinnen
·
ACM/IEEE Design Automation Conference (DAC)
·
85
Benchmarks for layout synthesis---evolution and current status
1991
·
Krzysztof Koźmiński
·
ACM/IEEE Design Automation Conference (DAC)
·
81
Cost minimization of partitions into multiple devices
1993
·
Roman Kužnar
, Franc Brglez
, et al.
·
ACM/IEEE Design Automation Conference (DAC)
·
68
PDF
Executable Workflows: A Paradigm For Collaborative Design On The Internet
1997
·
H. Lavana
, A. Khetawat
, et al.
·
ACM/IEEE Design Automation Conference (DAC)
·
54
PDF
Rectangular dualization and rectangular dissections
1988
·
K.A. Kozminski
, E. Kinnen
·
IEEE Transactions on Circuits and Systems
·
52
OASIS: a silicon compiler for semi-custom design
2002
·
G. Kedem
, F. Brglez
, et al.
·
Euro ASIC Conference (EURO ASIC)
·
12
OASIS: a silicon compiler for semi-custom design
2002
·
G. Kedem
, F. Brglez
, et al.
·
International Workshop on Rapid System Prototyping (RSP)
·
10
ASIC design with OASIS
2002
·
G. Kedem
, F. Brglez
, et al.
·
IEEE International Symposium on Circuits and Systems proceedings
·
6
A functionality fault model: feasibility and applications
2002
·
A. Zemva
, F. Brglez
, et al.
·
European Design and Test Conference
·
5
Synergy of synthesis and test (logic design)
2003
·
F. Brglez
, D. Bryan
, et al.
·
Biennial University/Government/Industry Microelectronics Symposium
·
1
Synergy of Synthesis and Test
1989
·
F. Brglez
, D. Bryan
, et al.
·
1
OASIS/sup R/ Application to Re-Synthesis of FPGA Designs as Standard Cell ASICs
2005
·
K. Kozminski
·
Southeastern Symposium on System Theory (SSST)
A heuristic global router for polycell layout
2003
·
V.K. De
, K. Kozminski
, et al.
·
Custom Integrated Circuits Conference
The Interlocking Bus Network For Fault-Tolerant Processor Arrays
1991
·
Markus G. Siegle
, Douglas S. Reeves
, et al.
·
Informatik-Fachberichte
Rectangular dualization for computer-aided design of vlsi integrated circuit floorplans (layout, hierarchical design)
1985
·
Krzysztof Koźmiński
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Works count:
20
Citation count:
2,589
H-index:
9
I10-index:
9
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