Author

Y. Monnet

Observed names: MONNET, Yannick, Monnet, Y., Yannick Monnet

Institution: Techniques of Informatics and Microelectronics for Integrated Systems Architecture

Observed institution: Techniques of Informatics and Microelectronics for Integrated Systems Architecture

OpenAlex ID: A5075979407

Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic

2006 · Y. Monnet, M. Renaudin, et al. · IEEE Transactions on Computers · 58

Hardening techniques against transient faults for asynchronous circuits

2005 · Y. Monnet, M. Renaudin, et al. · IEEE International On-Line Testing Symposium (IOLTS) · 46

Asynchronous circuits transient faults sensitivity evaluation

2005 · Y. Monnet, M. Renaudin, et al. · ACM/IEEE Design Automation Conference (DAC) · 34

Asynchronous circuits sensitivity to fault injection

2004 · Y. Monnet, M. Renaudin, et al. · IEEE International On-Line Testing Symposium (IOLTS) · 33

Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor

2006 · Y. Monnet, M. Renaudin, et al. · IEEE International On-Line Testing Symposium (IOLTS) · 15

Comparing transient-fault effects on synchronous and on asynchronous circuits

2009 · R. Possamai Bastos, Y. Monnet, et al. · IEEE International On-Line Testing Symposium (IOLTS) · 13

Case Study of a Fault Attack on Asynchronous DES Crypto-Processors

2006 · Yannick Monnet, Marc Renaudin, et al. · Lecture notes in computer science · 11

Asynchronous circuits transient faults sensitivity evaluation

2005 · Y. Monnet, M. Renaudin, et al. · ACM/IEEE Design Automation Conference (DAC) · 11

Asynchronous Design: Fault Robustness and Security Characteristics

2006 · M. Renaudin, Y. Monnet · IEEE International On-Line Testing Symposium (IOLTS) · 9

Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs

2007 · Y. Monnet, M. Renaudin, et al. · IEEE International On-Line Testing Symposium (IOLTS) · 8

An Asynchronous DES Crypto-Processor Secured against Fault Attacks

2005 · Monnet, Y., Renaudin, Marc, et al. · HAL · 3

Étude et modélisation de circuits résistants aux attaques non intrusives par injection de fautes

2007 · Y. Monnet · HAL · 2

PDF

A Methodology to Evaluate Transient-Fault Effects on Asynchronous and Synchronous Circuits

2009 · Possamai Bastos, Rodrigo, Monnet, Y., et al. · HAL · 1

Formal analysis of quasi delay insensitive circuits behavior in the presence of SEUs

2007 · Monnet, Y., Renaudin, Marc, et al. · HAL

Power consumption profile analysis of asynchronous QDI circuits

2007 · Rios, D., Folco, Bertrand, et al. · HAL

Study and modelling of secure circuits against non invasive fault injection attacks

2007 · MONNET, Yannick, RENAUDIN, Marc, et al. · OpenGrey (Institut de l'Information Scientifique et Technique)

Designing resistant asynchronous circuits against malicious fault injection

2005 · Bouesse, Ghislain, Fraidy, Monnet, Y., et al. · HAL

Secure asynchronous circuits design and prototyping

2005 · Renaudin, Marc, Bouesse, Ghislain, Fraidy, et al. · HAL

Secure asynchronous circuits for Smart-Card applications: Design and Methodologies

2005 · Bouesse, Ghislain, Fraidy, Monnet, Y., et al. · HAL

Analyse du comportement des circuits asynchrones en présence de fautes

2005 · Monnet, Y., Renaudin, M., et al. · HAL

Improving DPA and DFA resistance of circuits using asynchronous logic

2004 · Bouesse, Ghislain, Fraidy, Monnet, Y., et al. · HAL

Etude et modélisation de circuits résistants aux attaques par injection de fautes

2004 · Monnet, Y., Renaudin, M., et al. · HAL

Works count: 22

Citation count: 244

H-index: 9

I10-index: 8