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Surya Shankar Dan
Observed names:
S.S. Dan,
Surya S. Dan
Institution:
Birla Institute of Technology and Science - Hyderabad Campus
Observed institutions:
Birla Institute of Technology and Science - Hyderabad Campus,
École Polytechnique Fédérale de Lausanne,
Indian Institute of Science Bangalore,
Birla Institute of Technology and Science, Pilani
ORCID:
0000-0003-2767-4999
Observed ORCID:
0000-0003-2767-4999
OpenAlex ID:
A5076264641
TCAD simulation of SOI TFETs and calibration of non-local band-to-band tunneling model
2012
·
Arnab Biswas
, Surya Shankar Dan
, et al.
·
Microelectronic Engineering
·
148
An Efficient Ultra-Low-Power and Superior Performance Design of Ternary Half Adder Using CNFET and Gate-Overlap TFET Devices
2021
·
Sanjay Vidhyadharan
, Surya Shankar Dan
·
IEEE Transactions on Nanotechnology
·
29
Suppression of Ambipolar Behavior and Simultaneous Improvement in RF Performance of Gate-Overlap Tunnel Field Effect Transistor (GOTFET) Devices
2020
·
Ramakant Yadav
, Surya S. Dan
, et al.
·
Silicon
·
18
Experimental Demonstration of CeO 2 -Based Tunable Gated Memristor for RRAM Applications
2023
·
Soumi Saha
, Subhradeep Pal
, et al.
·
ACS Applied Electronic Materials
·
17
Demonstration of a 2-D SnS/MXene Nanohybrid Asymmetric Memristor
2022
·
Soumi Saha
, Vivek Adepu
, et al.
·
IEEE Transactions on Electron Devices
·
17
A nanoscale gate overlap tunnel FET (GOTFET) based improved double tail dynamic comparator for ultra-low-power VLSI applications
2019
·
Sanjay Vidhyadharan
, Ramakant Yadav
, et al.
·
Analog Integrated Circuits and Signal Processing
·
17
An advanced adiabatic logic using Gate Overlap Tunnel FET (GOTFET) devices for ultra-low power VLSI sensor applications
2019
·
Sanjay Vidhyadharan
, Ramakant Yadav
, et al.
·
Analog Integrated Circuits and Signal Processing
·
14
Engineering Oxygen Vacancies in CeO2 for High-Performance UV-Vis Photodetector
2023
·
Soumi Saha
, C. J. Keerthi
, et al.
·
IEEE Photonics Technology Letters
·
13
Design Considerations for Efficient Realization of Rectifiers in Microscale Wireless Power Transfer Systems: A Review
2022
·
Arun Mohan
, Saroj Mondal
, et al.
·
IEEE Sensors Journal
·
13
A Novel Extraction Method and Compact Model for the Steepness Estimation of FDSOI TFET Lateral Junction
2011
·
Surya S. Dan
, Arnab Biswas
, et al.
·
IEEE Electron Device Letters
·
13
Impact of energy quantisation in single electron transistor island on hybrid complementary metal oxide semiconductor– single electron transistor integrated circuits
2010
·
S.S. Dan
, S. Mahapatra
·
IET Circuits Devices & Systems
·
13
Light- and Pressure-Stimulated Silver Oxide (AgOx)-Based Memristors for In-Sensor Memory and Computing Applications
2024
·
Bishal Kumar Keshari
, Soumi Saha
, et al.
·
ACS Applied Electronic Materials
·
11
A novel ultra-low-power gate overlap tunnel FET (GOTFET) dynamic adder
2020
·
Sanjay Vidhyadharan
, Surya Shankar Dan
, et al.
·
International Journal of Electronics
·
11
Analysis of Energy Quantization Effects on Single-Electron Transistor Circuits
2010
·
Surya Shankar Dan
, Santanu Mahapatra
·
IEEE Transactions on Nanotechnology
·
11
Experimental demonstration of SnO₂ nanofiber-based memristors and their data-driven modeling for nanoelectronic applications
2023
·
Soumi Saha
, Madadi Chetan Kodand Reddy
, et al.
·
Chip
·
10
Innovative multi-threshold gate-overlap tunnel FET (GOTFET) devices for superior ultra-low power digital, ternary and analog circuits at 45-nm technology node
2020
·
Ramakant Yadav
, Surya S. Dan
, et al.
·
Journal of Computational Electronics
·
10
Part II: Benchmarking the Performance of Optimized TFET-Based Circuits with the Standard 45 nm CMOS Technology Using Device & Circuit Co-simulation Methodology
2019
·
Sanjay Vidhyadharan
, Ramakant
, et al.
·
Springer proceedings in physics
·
10
An Efficient Design Approach for Implementation of 2 Bit Ternary Flash ADC Using Optimized Complementary TFET Devices
2019
·
Sanjay Vidhyadharan
, Ramakant Ramakant
, et al.
·
International Conference on VLSI Design
·
10
Impact of Energy Quantization on the Performance of Current-Biased SET Circuits
2009
·
Surya Shankar Dan
, Santanu Mahapatra
·
IEEE Transactions on Electron Devices
·
9
Novel gate-overlap tunnel FET based innovative ultra-low-power ternary flash ADC
2020
·
Sanjay Vidhyadharan
, Surya Shankar Dan
, et al.
·
Integration
·
7
Assessment of SET Logic Robustness Through Noise Margin Modeling
2008
·
Chaitanya Sathe
, Surya Shankar Dan
, et al.
·
IEEE Transactions on Electron Devices
·
7
PDF
Emulation of versatile tunable universal mem-elements design and its application
2025
·
Niranjan Raj
, Anshul Awasthi
, et al.
·
AEU - International Journal of Electronics and Communications
·
6
Mimicking somatic behavior of neurons using the integrate and fire model of 2D SnS memristive switching characteristics
2024
·
Soumi Saha
, Vivek Adepu
, et al.
·
Applied Physics Letters
·
6
An innovative ultra-low voltage GOTFET based regenerative-latch Schmitt trigger
2020
·
Sanjay Vidhyadharan
, Surya Shankar Dan
, et al.
·
Microelectronics Journal
·
6
Part I: Optimization of the Tunnel FET Device Structure for Achieving Circuit Performance Better Than the Current Standard 45 nm CMOS Technology
2019
·
Ramakant
, Sanjay Vidhyadharan
, et al.
·
Springer proceedings in physics
·
6
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Works count:
43
Citation count:
453
H-index:
11
I10-index:
18
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