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Mark Zwoliński

Observed names: A. Zwolinski, M Zwolinski, M. ZWOLINSKI, M. Zwolinski, M. Zwoliński, Mark Zwolifiski, Mark Zwolinski, Mark Zwolinskiz, Zwolinski, Mark, Zwoliński, Mark
ORCID: 0000-0002-2230-625X
Observed ORCID: 0000-0002-2230-625X
OpenAlex ID: A5077466475
Electrically conductive adhesives for surface mount solder replacement
1996 · M. Zwolinski, J. Hickman, et al. · IEEE Transactions on Components Packaging and Manufacturing Technology Part C · 144
Overview of PUF-based hardware security solutions for the internet of things
2016 · Basel Halak, Mark Zwolinski, et al. · IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) · 112
Digital System Design with VHDL (2nd Edition)
2000 · Mark Zwoliński · 106
A beginning in the reversible logic synthesis of sequential circuits
2005 · Himanshu Thapliyal, M.B. Srinivas, et al. · ePrints Soton (University of Southampton) · 91
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VLSI Circuit Simulation and Optimization
1996 · Van ̆ Litovski, Mark Zwoliński · ePrints Soton (University of Southampton) · 83
Evaluation of Dynamic Voltage and Frequency Scaling as a Differential Power Analysis Countermeasure
2007 · Karthik Baddam, Mark Zwolinski · International Conference on VLSI Design · 78
Mutual information theory for adaptive mixture models
2001 · Zheng Rong Yang, M. Zwolinski · IEEE Transactions on Pattern Analysis and Machine Intelligence · 72
Applying a robust heteroscedastic probabilistic neural network to analog fault detection and classification
2000 · Zheng Rong Yang, M. Zwolinski, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 58
Overview of SPICE-like circuit simulation algorithms
1994 · K.G. Nichols, T.J. Kazmierski, et al. · IEE Proceedings - Circuits Devices and Systems · 49
Reversible Logic to Cryptographic Hardware: A New Paradigm
2006 · Himanshu Thapliyal, Mark Zwolinski · IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) · 44
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Simultaneous optimisation of dynamic power, area and delay in behavioural synthesis
2000 · A.C. Williams, A.D. Brown, et al. · IEE Proceedings - Computers and Digital Techniques · 41
Analytical transient response and propagation delay model for nanoscale CMOS inverter
2009 · Yangang Wang, Mark Zwolinski · IEEE International Symposium on Circuits and Systems proceedings · 39
Analogue electronic circuit diagnosis based on ANNs
2006 · Vančo Litovski, Miona Andrejević, et al. · Microelectronics Reliability · 39
Dynamic Voltage Scaling Aware Delay Fault Testing
2006 · N.B. Zain Ali, M. Zwolinski, et al. · IEEE European Test Symposium (ETS) · 35
Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations
2003 · S.J. Spinks, C.D. Chalk, et al. · Journal of Electronic Testing · 27
Fault Modeling and Simulation Using VHDL-AMS
1998 · A. J. Perkins, M. Zwolinski, et al. · Analog Integrated Circuits and Signal Processing · 27
A Low-Cost, Radiation-Hardened Method for Pipeline Protection in Microprocessors
2015 · Yang Lin, Mark Zwolinski, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 26
Network-on-chip: Current issues and challenges
2015 · Manoj Singh Gaur, Vijay Laxmi, et al. · International Symposium on VLSI Design and Test (VDAT) · 26
Divided Backend Duplication Methodology for Balanced Dual Rail Routing
2008 · Karthik Baddam, Mark Zwolinski · Lecture notes in computer science · 26
A reliable PUF in a dual function SRAM
2019 · Mohd Syafiq Mispan, Shengyu Duan, et al. · Integration · 24
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TCO-PUF: A subthreshold physical unclonable function
2015 · Mohd Syafiq Mispan, Basel Halak, et al. · Conference on Ph.D. Research in Microelectronics and Electronics · 24
Hardware performance counters for system reliability monitoring
2017 · Elena Woo Lai Leng, Mark Zwolinski, et al. · IEEE International Verification and Security Workshop (IVSW) · 23
Generation and verification of tests for analogue circuits subject to process parameter deviations
2002 · S.J. Spinks, C.D. Chalk, et al. · Proceedings · 23
Cost-efficient design for modeling attacks resistant PUFs
2018 · Mohd Syafiq Mispan, Haibo Su, et al. · Design, Automation, and Test in Europe · 22
Parallel Sparse Matrix Solution for Circuit Simulation on FPGAs
2014 · Tarek Nechma, Mark Zwolinski · IEEE Transactions on Computers · 22
Works count: 283
Citation count: 2,257
H-index: 23
I10-index: 59
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