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Viveka Konandur Rajanna

Observed names: K R Viveka, K.R. Viveka, Viveka Konandur, Viveka Rajanna
ORCID: 0000-0001-5353-7109
Observed ORCID: 0000-0001-5353-7109
OpenAlex ID: A5077965424
In-Memory Unified TRNG and Multi-Bit PUF for Ubiquitous Hardware Security
2021 · Sachin Taneja, Viveka Konandur Rajanna, et al. · IEEE Journal of Solid-State Circuits · 76
36.1 Unified In-Memory Dynamic TRNG and Multi-Bit Static PUF Entropy Generation for Ubiquitous Hardware Security
2021 · Sachin Taneja, Viveka Konandur Rajanna, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 58
ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm
2023 · Joydeep Basu, Sachin Taneja, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 14
Single-Antenna Backscattered BLE5 Transmitter with up to 97m Range, 10.6 μW Peak Power for Purely-Harvested Green Systems
2023 · Karim Ali Ahmed, Ruiyuan Yang, et al. · European Solid-State Circuits Conference (ESSCIRC) · 10
DDPMnet: All-Digital Pulse Density-Based DNN Architecture with 228 Gate Equivalents/MAC Unit, 28-TOPS/W and 1.5-TOPS/mm2 in 40nm
2022 · Animesh Gupta, Viveka Konandur, et al. · Custom Integrated Circuits Conference · 7
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Fully-Digital Broadband Calibration-Less Impedance Monitor for Probe Insertion Detection against Power Analysis Attacks
2022 · Viveka Konandur Rajanna, Himadri Singh Raghav, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 6
A Variation-Tolerant Replica-Based Reference-Generation Technique for Single-Ended Sensing in Wide Voltage-Range SRAMs
2015 · Viveka Konandur Rajanna, Bharadwaj Amrutur · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 6
On-Chip Links With Energy-Quality Tradeoff in Error-Resilient and Machine Learning Applications
2021 · Viveka Konandur Rajanna, Massimo Alioto · IEEE Journal of Solid-State Circuits · 5
Low-Swing Links with Dynamic Energy-Quality Trade-off for Error-Resilient Applications
2019 · Viveka Konandur Rajanna, Massimo Alioto · Custom Integrated Circuits Conference · 5
SRAM Physically Unclonable Function Extracting Static Entropy from Every Bitcell Transistor for 6 bit/bitcell and Data Fingerprinting Capability for Provenance Assurance
2024 · Tianqi Wang, Joydeep Basu, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 3
122.7 TOPS/W Stdcell-Based DNN Accelerator Based on Transition Density Data Representation, Clock-Less MAC Operation, Pseudo-Sparsity Exploitation in 40 nm
2024 · Animesh Gupta, Japesh Vohra, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 3
SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-On Sensing with 109 TOPS/mm2 and 749-1,459 TOPS/W in 28nm
2021 · Viveka Konandur Rajanna, Sachin Taneja, et al. · European Solid-State Circuits Conference (ESSCIRC) · 3
Energy Efficient Memory Decoder Design for Ultra-low Voltage Systems
2014 · K.R. Viveka, Bharadwaj Amrutur · International Conference on VLSI Design · 3
Digitally controlled variation tolerant timing generation technique for SRAM sense amplifiers
2013 · K R Viveka, Bharadwaj Amrutur · Asia Symposium on Quality Electronic Design · 3
SRAM Static Entropy Extraction From Every Single Transistor in Unmodified Bitcell and Data Fingerprinting for Provenance Assurance
2025 · Tianqi Wang, Joydeep Basu, et al. · IEEE Journal of Solid-State Circuits · 1
Energy-Efficient Computation in Constrained Systems with Machine Learning Workloads
2023 · Viveka Konandur Rajanna · IEEE International Symposium on Smart Electronic Systems (iSES) · 1
Visual Content-Agnostic Novelty Detection Engine with 2.4 pJ/pixel Energy and Two-Order of Magnitude DNN Activity Reduction in 40 nm
2023 · Animesh Gupta, Sayan Kumar, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 1
SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-On Sensing with 109 TOPS/mm2 and 749-1,459 TOPS/W in 28nm
2021 · Viveka Konandur Rajanna, Sachin Taneja, et al. · European Solid-State Device Research Conference · 1
Fully-Digital Self-Calibrating Decoder with Sub-µW, 1.6fJ/convstep and 0.0075mm2 per Receptor for Scaling to Human-Like Tactile Sensing Density
2021 · Prachi Agarwal, Viveka Konandur Rajanna, et al. · Symposium on VLSI Circuits · 1
Low Power Pipelined TCAM Employing Mismatch Dependent Power Allocation Technique
2007 · K.R. Viveka, Abhilasha Kawle, et al. · International Conference on VLSI Design · 1
Approximate DCT using Scaling Factor Optimization for Error-Resilient Applications
2026 · Pranav Kumar VS, Lakshmi Soumya Burle, et al. · IEEE International Symposium on Circuits and Systems proceedings
A 109TOPS/mm2 and 749-1,459TOPS/W SRAM Buffer with In-Memory Inference and Prediction-Less Bitline Activity Reduction in 28nm
2021 · Viveka Konandur Rajanna, Sachin Taneja, et al.
Fully-Digital Self-Calibrating Decoder with Sub-µW, 1.6fJ-convstep and 0.0075mm2 per Receptor for Scaling to Human-Like Tactile Sensing Density
2021 · Prachi Agarwal, Viveka Konandur, et al. · National University of Singapore
Design and Characterization of SRAMs for Ultra Dynamic Voltage Scalable (U-DVS) Systems
2016 · K.R. Viveka
Pressure Sensor Based Tsunami Detection System: A Laboratory Study
2006 · K.R. Viveka, S. Ramgopal, et al. · Proceedings of IEEE Sensors/Proceedings of IEEE Sensors ...
Works count: 25
Citation count: 208
H-index: 6
I10-index: 4
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