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Author

A. Fedeli

Observed name: Andrea Fedeli
Observed institution: STMicroelectronics (Italy)
OpenAlex ID: A5078157123
Properties Incompleteness Evaluation by Functional Verification
2007 · Andrea Fedeli, Franco Fummi, et al. · IEEE Transactions on Computers · 42
Hybrid, Incremental Assertion-Based Verification for TLM Design Flows
2007 · Nicola Bombieri, Franco Fummi, et al. · IEEE Design & Test of Computers · 26
On the use of a high-level fault model to check properties incompleteness
2003 · F. Fummi, G. Pravadelli, et al. · ACM/IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE) · 22
On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling
2005 · Nicola Bombieri, Andrea Fedeli, et al. · International Workshop on Microprocessor Test and Verification (MTV) · 21
SC2SCFL: Automated SystemC to $SystemC^{\mathbb{FL}}$ Translation
2007 · Ka Lok Man, Andrea Fedeli, et al. · Springer eBooks · 11
A 1000X speed up for properties completeness evaluation
2003 · A. Castelnuovo, A. Fedeli, et al. · Proceedings · 6
A verification methodology for reconfigurable systems
2006 · M. Borgatti, A. Fedeli, et al. · International Workshop on Microprocessor Test and Verification (MTV) · 4
An error simulation based approach to measure error coverage of formal properties
2002 · P. Azzoni, A. Fedeli, et al. · ACM Great Lakes Symposium on VLSI (GLSVLSI) · 2
Extended abstract: on the property-based verification in SoC design flow founded on transaction level modeling
2005 · N. Bombieri, A. Fedeli, et al. · ACM/IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE) · 1
On the Use of a Fault Model to Validate the Completeness of a Set of Properties
2002 · A. Fedeli, Franco Fummi, et al. · International Workshop on Microprocessor Test and Verification (MTV) · 1
Symbad: Formal Verification in System Level-based Design (Extended Version)
2005 · A. Fedeli, Franco Fummi, et al.
Concrete impact of formal verification on quality in IP design and implementation
2002 · U. Ressi, A. Fedeli, et al. · International Symposium on Quality Electronic Design (ISQED)
Formal verification techniques: industrial status and perspectives
2002 · I. Moussa, R. Pacalet, et al. · Design, Automation, and Test in Europe
Highlights of RTL to gate comparison by the use of formality
2002 · Ka Lok Man, A. Fedeli, et al. · TU/e Research Portal
An error simulation based approach to measure error coverage of formal properties
2002 · P. Azzoni, A. Fedeli, et al. · ACM Great Lakes Symposium on VLSI (GLSVLSI)
Works count: 17
Citation count: 136
H-index: 6
I10-index: 5
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