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Author

Ming Ling

Observed names: Ling Ming, Ling, Ming, Ming LING
ORCID: 0000-0002-8866-7189
Observed ORCID: 0000-0002-8866-7189
OpenAlex ID: A5078395317
Vina-GPU 2.0: Further Accelerating AutoDock Vina and Its Derivatives with Graphics Processing Units
2023 · Ji Ding, Shidi Tang, et al. · Journal of Chemical Information and Modeling · 142
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An Active Mobile Charging and Data Collection Scheme for Clustered Sensor Networks
2019 · Kaiyang Liu, Jun Peng, et al. · IEEE Transactions on Vehicular Technology · 66
Effectiveness Analysis of Multiple Initial States Simulated Annealing Algorithm, a Case Study on the Molecular Docking Tool AutoDock Vina
2023 · Xingxing Zhou, Ming Ling, et al. · IEEE Transactions on Computational Biology and Bioinformatics · 31
An embedded implementation of CNN-based hand detection and orientation estimation algorithm
2019 · Li Yang, Zhi Qi, et al. · Machine Vision and Applications · 29
Vina-FPGA: A Hardware-Accelerated Molecular Docking Tool With Fixed-Point Quantization and Low-Level Parallelism
2022 · Ming Ling, Qingde Lin, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 20
TS Cache: A Fast Cache With Timing-Speculation Mechanism Under Low Supply Voltages
2019 · Shan Shen, Tianxiang Shao, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 19
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An artificial neural network model of LRU-cache misses on out-of-order embedded processors
2017 · Kecheng Ji, Ming Ling, et al. · Microprocessors and Microsystems · 17
MLoF: Machine Learning Accelerators for the Low-Cost FPGA Platforms
2021 · Ruiqi Chen, Tianyu Wu, et al. · Applied Sciences · 13
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AFEC: An analytical framework for evaluating cache performance in out-of-order processors
2017 · Kecheng Ji, Ming Ling, et al. · Design, Automation, and Test in Europe · 13
Vina-FPGA-Cluster: Multi-FPGA Based Molecular Docking Tool With High-Accuracy and Multi-Level Parallelism
2024 · Ming Ling, Zhihao Feng, et al. · IEEE Transactions on Biomedical Circuits and Systems · 11
Does the ISA Really Matter? A Simulation Based Investigation
2019 · Ming Ling, Xin Xu, et al. · IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM) · 11
Implementation of a BIST scheme for ADC test
2003 · Wu Guanglin, Rao Jin, et al. · IEEE International Conference on ASIC (ASICON) · 10
Using the first-level cache stack distance histograms to predict multi-level LRU cache misses
2017 · Kecheng Ji, Ming Ling, et al. · Microprocessors and Microsystems · 9
A wireless network based on the combination of Zigbee and GPRS
2008 · Shen Lin, Shi xiangquan, et al. · IEEE International Conference on Networking, Sensing and Control (ICNSC) · 9
Diff-Acc: An Efficient FPGA Accelerator for Unconditional Diffusion Models
2025 · Shidi Tang, Ruiqi Chen, et al. · ACM Transactions on Embedded Computing Systems · 8
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A Timing Yield Model for SRAM Cells at Sub/Near-Threshold Voltages Based on a Compact Drain Current Model
2022 · Shan Shen, Peng Cao, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 8
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Fast modeling L2 cache reuse distance histograms using combined locality information from software traces
2020 · Ming Ling, Jiancong Ge, et al. · Journal of Systems Architecture · 8
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Lowering the Hit Latencies of Low Voltage Caches Based on the Cross-Sensing Timing Speculation SRAM
2019 · Ming Ling, Xiaojing Shang, et al. · IEEE Access · 8
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An Analytical Cache Performance Evaluation Framework for Embedded Out-of-Order Processors Using Software Characteristics
2018 · Kecheng Ji, Ming Ling, et al. · ACM Transactions on Embedded Computing Systems · 7
Ultra8T: A sub-threshold 8T SRAM with leakage detection
2024 · Shan Shen, Hao Xu, et al. · Integration · 6
RRS cache: a low voltage cache based on timing speculation SRAM with a reuse-aware cacheline remapping mechanism
2019 · Xiaojing Shang, Ming Ling, et al. · International Symposium on Memory Systems (MEMSYS) · 6
Detecting the phase behavior on cache performance using the reuse distance vectors
2018 · Shan Shen, Ming Ling, et al. · Journal of Systems Architecture · 6
A mechanistic model of memory level parallelism fed with cache miss rates
2017 · Qin Wang, Kecheng Ji, et al. · IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM) · 6
FPGA-Based Approximate Multiplier for FP8
2025 · Ruiqi Chen, Yangxintong Lyu, et al. · IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) · 5
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A Fast Cross-Layer Dynamic Power Estimation Method by Tracking Cycle-Accurate Activity Factors With Spark Streaming
2021 · Leilei Jin, Wenjie Fu, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 5
Works count: 112
Citation count: 567
H-index: 11
I10-index: 12
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