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Yasuhiko Taito

Observed names: Y. Taito, Yasuhiko TAITO
ORCID: 0000-0001-6676-4853
Observed ORCID: 0000-0001-6676-4853
OpenAlex ID: A5079433991
7.3 A 28nm embedded SG-MONOS flash macro for automotive achieving 200MHz read operation and 2.0MB/S write throughput at Ti, of 170°C
2015 · Yasuhiko Taito, Masaya Nakano, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 35
A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170C
2015 · Yasuhiko Taito, Takashi Kono, et al. · IEEE Journal of Solid-State Circuits · 31
15.8 A 22nm 10.8Mb Embedded STT-MRAM Macro Achieving over 200MHz Random-Read Access and a 10.4MB/s Write Throughput with an In-Field Programmable 0.3Mb MTJ-OTP for High-End MCUs
2024 · Tomoya Ogawa, Ken Matsubara, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 29
7.6 A 90nm embedded 1T-MONOS flash macro for automotive applications with 0.07mJ/8kB rewrite energy and endurance over 100M cycles under Tj of 175°C
2016 · Hidenori Mitani, Ken Matsubara, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 19
A 22nm 32Mb Embedded STT-MRAM Macro Achieving 5.9ns Random Read Access and 5.8MB/s Write Throughput at up to Tj of 150 °C
2022 · Takahiro Shimoi, Ken Matsubara, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 13
A 22-nm 32-Mb Embedded STT-MRAM Macro Achieving 5.9-ns Random Read Access and 7.4-MB/s Write Throughput at up to 150 °C
2023 · Takahiro Shimoi, Ken Matsubara, et al. · IEEE Journal of Solid-State Circuits · 12
A high density memory for SoC with a 143MHz SRAM interface using sense-synchronized-read/write
2003 · Y. Taito, T. Tanizaki, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 12
Essential Roles, Challenges and Development of Embedded MCU Micro-Systems to Innovate Edge Computing for the IoT/AI Age
2020 · Takashi KONO, Yasuhiko TAITO, et al. · IEICE Transactions on Electronics · 11
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A 24-MB Embedded Flash System Based on 28-nm SG-MONOS Featuring 240-MHz Read Operations and Robust Over-the-Air Software Update for Automotive Applications
2019 · Akihiko Kanda, Takashi Kono, et al. · IEEE Solid-State Circuits Letters · 11
An embedded DRAM hybrid macro with auto signal management and enhanced-on-chip tester
2002 · N. Watanabe, F. Morishita, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 11
A 40-nm Embedded SG-MONOS Flash Macro for High-End MCU Achieving 200-MHz Random Read Operation and 7.91-Mb/mm2 Density With Charge-Assisted Offset Cancellation Sense Amplifier
2022 · Masaya Nakano, Yoshinobu Kaneda, et al. · IEEE Journal of Solid-State Circuits · 10
A 20Mb Embedded STT-MRAM Array Achieving 72% Write Energy Reduction with Self-termination Write Schemes in 16nm FinFET Logic Process
2021 · T. Ito, T. Saito, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 6
An embedded DRAM with a 143-MHz SRAM interface using a sense-synchronized read/write
2003 · Y. Taito, T. Tanizaki, et al. · IEEE Journal of Solid-State Circuits · 6
A 24MB Embedded Flash System Based on 28nm SG-MONOS Featuring 240MHz Read Operations and Robust Over-The-Air Software Update for Automotive
2019 · Akihiko Kanda, Takashi Kurafuji, et al. · Symposium on VLSI Circuits · 4
A 40nm Embedded SG-MONOS Flash Macro for High-end MCU Achieving 200MHz Random Read Operation and 7.91Mb/mm2 Density with Charge Assisted Offset Cancellation Sense Amplifier
2021 · Masaya Nakano, Yoshinobu Kaneda, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 3
SONOS Split-Gate eFlash Memory
2017 · Takashi Ito, Yasuhiko Taito · Integrated circuits and systems · 3
An Embedded DRAM Hybrid Macro with Auto Signal Management and Enhanced-on-Chip Tester
2003 · Naoya Watanabe, Fukashi Morishita, et al. · IEICE Transactions on Electronics · 3
Trends in Embedded Volatile and Non-Volatile Memories for Scalable Edge AI Applications
2025 · Tomoya Saito, Koichi Nose, et al. · Technical digest - International Electron Devices Meeting/Technical digest
Introduction to the Special Section on the 2021 IEEE International Solid-State Circuits Conference (ISSCC)
2021 · Amir Amirkhany, Tanay Karnik, et al. · IEEE Journal of Solid-State Circuits
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Session 30 Overview: Non-Volatile Memories
2021 · Yasuhiko Taito, Violante Moschiano, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
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A 90nm Embedded 1T-MONOS Flash Macro for Automotive Applications with 0.07mJ/8kB Rewrite Energy and Endurance Over 100M Cycles Under Tj of 175°C
2016 · Satoru Nakanishi, Hidenori Mitani, et al. · IEICE Technical Report; IEICE Tech. Rep.
A Low Power Embedded DRAM Macro for Battery-Operated LSIs
2003 · Takeshi Fujino, Akira Yamazaki, et al. · IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences
Signal Management and Enhanced-on-Chip Tester
2001 · Naoya Watanabe, Fukashi Morishita, et al.
Microfabrication of nonlinear optical organic crystals using an inorganic photoresist
1994 · Yasuhiko Taito, Takashi Kondo, et al. · Elsevier eBooks
Works count: 24
Citation count: 219
H-index: 10
I10-index: 11
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