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Satish Maheshwaram

Observed names: Maheshwaram Satish, S Maheshwaram, S. Maheshwaram
ORCID: 0000-0002-1760-1545
Observed ORCID: 0000-0002-1760-1545
OpenAlex ID: A5079475933
Virtual Mouse Control Using Colored Finger Tips and Hand Gesture Recognition
2020 · Vantukala VishnuTeja Reddy, Thumma Dhyanchand, et al. · IEEE-HYDCON · 60
Radiation Effects in Si-NW GAA FET and CMOS Inverter: A TCAD Simulation Study
2012 · Gaurav Kaushal, S. S. Rathod, et al. · IEEE Transactions on Electron Devices · 47
Vertical Silicon Nanowire Gate-All-Around Field Effect Transistor Based Nanoscale CMOS
2011 · Satish Maheshwaram, S. K. Manhas, et al. · IEEE Electron Device Letters · 42
A Degradation Model of Double Gate and Gate-All-Around MOSFETs With Interface Trapped Charges Including Effects of Channel Mobile Charge Carriers
2014 · Ravi Shankar, Gaurav Kaushal, et al. · IEEE Transactions on Device and Materials Reliability · 33
Effect of Load Capacitance and Input Transition Time on FinFET Inverter Capacitances
2014 · Archana Pandey, Swati Raycha, et al. · IEEE Transactions on Electron Devices · 32
Vertical Nanowire CMOS Parasitic Modeling and its Performance Analysis
2013 · Satish Maheshwaram, S. K. Manhas, et al. · IEEE Transactions on Electron Devices · 31
A novel circular double-gate SOI MOSFET with raised source/drain
2021 · Sagar Kallepelli, Satish Maheshwaram · Semiconductor Science and Technology · 25
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Reduction of GIDL Using Dual Work-Function Metal Gate in DRAM
2016 · S. K. Gautam, S. Maheshwaram, et al. · IEEE International Memory Workshop (IMW) · 25
Compact NBTI Reliability Modeling in Si Nanowire MOSFETs and Effect in Circuits
2017 · Om Prakash, Swen Beniwal, et al. · IEEE Transactions on Device and Materials Reliability · 20
Optimization of Sidewall Spacer Engineering at Sub-5 nm Technology Node For JL-Nanowire FET: Digital/Analog/RF/Circuit Perspective
2023 · Chandana Anguru, Vamsi Krishna Aryasomayajula, et al. · ECS Journal of Solid State Science and Technology · 17
Design and Performance Optimization of Junctionless Bottom Spacer FinFET for Digital/Analog/RF Applications at Sub-5nm Technology Node
2023 · Sresta Valasa, K. V. Ramakrishna, et al. · ECS Journal of Solid State Science and Technology · 17
Impact of series resistance on Si nanowire MOSFET performance
2013 · G. Kaushal, S. K. Manhas, et al. · Journal of Computational Electronics · 16
Low power SRAM design for 14 nm GAA Si-nanowire technology
2015 · Gaurav Kaushal, H. Jeong, et al. · Microelectronics Journal · 12
Device Circuit Co-Design Issues in Vertical Nanowire CMOS Platform
2012 · Satish Maheshwaram, S. K. Manhas, et al. · IEEE Electron Device Letters · 12
Dielectric Material and Thermal Optimization in Sidewall Spacer Design for Junctionless Nanosheet FETs at Sub- 5 nm Technology Node: An Insight into Device and Circuit Performance
2024 · Vanitha Indhur, Uma Maheshwari Dupati, et al. · ECS Journal of Solid State Science and Technology · 10
Performance and Variability Analysis of SiNW 6T-SRAM Cell Using Compact Model With Parasitics
2017 · Om Prakash, Satish Maheshwaram, et al. · IEEE Transactions on Nanotechnology · 9
Performance Analysis of Sub 10 nm Double Gate Circular MOSFET
2022 · Kallepelli Sagar, Satish Maheshwaram · Silicon · 8
Compact model for vertical silicon nanowire based device simulation and circuit design
2015 · M. Sharma, S. Maheshwaram, et al. · International SoC Design Conference · 8
Novel Design Methodology Using $L_{\bf EXT}$ Sizing in Nanowire CMOS Logic
2014 · G. Kaushal, S. K. Manhas, et al. · IEEE Transactions on Nanotechnology · 7
A Novel Vertically Stacked Circular Nanosheet FET for High-Performance Applications
2022 · Sagar Kallepelli, Satish Maheshwaram · ECS Journal of Solid State Science and Technology · 6
Impact of Time Zero Variability and BTI Reliability on SiNW FET-Based Circuits
2019 · Om Prakash, S. Maheshwaram, et al. · IEEE Transactions on Device and Materials Reliability · 6
Benchmarking and Optimization of Circular Double Gate Transistor (CDGT) for Sub 10 nm Nodes
2023 · Kallepelli Sagar, Satish Maheshwaram · Silicon · 5
Subject Tracking with Camera Movement Using Single Board Computer
2020 · Sahil Babu, Balabhadruni Shiva Pragathi, et al. · IEEE-HYDCON · 5
Design and performance analysis of double gate vertically stacked MoS2 nanosheet field effect transistor
2024 · Srikanth Rudravaram, Rajendra P Shukla, et al. · Physica Scripta · 4
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FinFET device Capacitances: Impact of input transition time and output load
2013 · Archana Pandey, Swati Raycha, et al. · IEEE International Nanoelectronics Conference · 4
Works count: 55
Citation count: 495
H-index: 12
I10-index: 15
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