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Sanroku Tsukamoto

Observed names: S. Tsukamoto, Sanroku TSUKAMOTO, Tsukamoto, Sanroku
Institution: Fujitsu (Japan)
OpenAlex ID: A5079527103
Split capacitor DAC mismatch calibration in successive approximation ADC
2009 · Yanfei Chen, Xiaolei Zhu, et al. · Custom Integrated Circuits Conference · 158
A 10-b 50-MS/s 820-$\mu $W SAR ADC With On-Chip Digital Calibration
2010 · Masato Yoshioka, Kiyoshi Ishikawa, et al. · IEEE Transactions on Biomedical Circuits and Systems · 131
A 10b 50MS/s 820µW SAR ADC with on-chip digital calibration
2010 · Masato Yoshioka, Kiyoshi Ishikawa, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 105
An Accelerator Architecture for Combinatorial Optimization Problems
2017 · Sanroku Tsukamoto, Takatsu Motomu, et al. · Fujitsu Scientific and Technical Journal · 93
Ising-Model Optimizer with Parallel-Trial Bit-Sieve Engine
2017 · Satoshi Matsubara, Hirotaka Tamura, et al. · Advances in intelligent systems and computing · 66
A CMOS 6-b, 400-MSample/s ADC with error correction
1998 · S. Tsukamoto, W.G. Schofield, et al. · IEEE Journal of Solid-State Circuits · 54
A 9b 100MS/s 1.46mW SAR ADC in 65nm CMOS
2009 · Yanfei Chen, Sanroku Tsukamoto, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 40
A 0.8V 10b 8OMS/s 6.5mW Pipelined ADC with Regulated Overdrive Voltage Biasing
2007 · Masato Yoshioka, Masahiro Kudo, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 31
A 6b 3GS/s flash ADC with background calibration
2009 · Masashi Kijima, Kenji Ito, et al. · Custom Integrated Circuits Conference · 29
A CMOS 6-b, 200 MSample/s, 3 V-supply A/D converter for a PRML read channel LSI
1996 · S. Tsukamoto, I. Dedic, et al. · IEEE Journal of Solid-State Circuits · 27
Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC
2010 · Yanfei CHEN, Xiaolei ZHU, et al. · IEICE Transactions on Electronics · 21
Dynamic Architecture and Frequency Scaling in 0.8–1.2 GS/s 7 b Subranging ADC
2015 · Kentaro Yoshioka, Ryo Saito, et al. · IEEE Journal of Solid-State Circuits · 18
A 10b 50MS/s 820uW SAR ADC with on-chip digital calibration
2010 · Sanroku Tsukamoto · IEICE Technical Report; IEICE Tech. Rep. · 18
32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS
2013 · Y. Doi, T. Shibasaki, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 17
A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array
2012 · Xiaolei Zhu, Yanfei Chen, et al. · International Symposium on VLSI Design, Automation and Test · 16
A 6-bit, 1-GS/s, 9.9-mW, Interpolated Subranging ADC in 65-nm CMOS
2014 · Takumi Danjo, Masato Yoshioka, et al. · IEEE Journal of Solid-State Circuits · 13
A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process
2013 · Yoshiyasu Doi, Takayuki Shibasaki, et al. · IEEE Journal of Solid-State Circuits · 11
A dynamic offset control technique for comparator design in scaled CMOS technology
2008 · Xiaolei Zhu, Yanfei Chen, et al. · Custom Integrated Circuits Conference · 11
7-bit 0.8–1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique
2014 · Kentaro Yoshioka, Ryo Saito, et al. · Symposium on VLSI Circuits · 6
32 Gb/s Data-Interpolator Receiver with 2-tap DFE in 28-nm CMOS
2013 · Yoshiyasu Doi, Takayuki Shibasaki, et al. · IEICE Technical Report; IEICE Tech. Rep. · 4
A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology
2010 · Xiaolei ZHU, Yanfei CHEN, et al. · IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences · 4
A 9-bit 100-MS/s 1.46-mW Tri-Level SAR ADC in 65 nm CMOS
2010 · Yanfei CHEN, Sanroku TSUKAMOTO, et al. · IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences · 3
A 1 GHz CMOS comparator with dynamic offset control technique
2009 · Xiaolei Zhu, Sanroku Tsukamoto, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 3
A 6b, 1GS/s, 9.9mW interpolated subranging ADC in 65nm CMOS
2012 · T. Danjo, M. Yoshioka, et al. · International Symposium on VLSI Design, Automation and Test · 2
A 9-bit 100MS/s SAR ADC with Digitally Assisted Background Calibration
2012 · Xiaolei ZHU, Yanfei CHEN, et al. · IEICE Transactions on Electronics · 2
Works count: 32
Citation count: 885
H-index: 15
I10-index: 18
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