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Sungju Ryu

Observed names: Ryu Sungju, Ryu, Sungju
Institution: Sogang University
ORCID: 0000-0002-0254-391X
Observed ORCID: 0000-0002-0254-391X
OpenAlex ID: A5079596428
BitBlade: Energy-Efficient Variable Bit-Precision Hardware Accelerator for Quantized Neural Networks
2022 · Sungju Ryu, Hyungjun Kim, et al. · IEEE Journal of Solid-State Circuits · 67
BitBlade: Area and Energy-Efficient Precision-Scalable Neural Network Accelerator with Bitwise Summation
2019 · Sungju Ryu, Hyungjun Kim, et al. · ACM/IEEE Design Automation Conference (DAC) · 59
Configurable BCAM/TCAM Based on 6T SRAM Bit Cell and Enhanced Match Line Clamping
2019 · Jongeun Koo, Eunhwan Kim, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 22
Feedforward-Cutset-Free Pipelined Multiply–Accumulate Unit for the Machine Learning Accelerator
2018 · Sungju Ryu, Naebeom Park, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 21
High-throughput Near-Memory Processing on CNNs with 3D HBM-like Memory
2021 · Naebeom Park, Sungju Ryu, et al. · ACM Transactions on Design Automation of Electronic Systems · 20
Algorithm/Hardware Co-Design for In-Memory Neural Network Computing with Minimal Peripheral Circuit Overhead
2020 · Hyungjun Kim, Yulhwa Kim, et al. · ACM/IEEE Design Automation Conference (DAC) · 19
Mobileware: A High-Performance MobileNet Accelerator with Channel Stationary Dataflow
2021 · Sungju Ryu, Youngtaek Oh, et al. · International Conference on Computer Aided Design · 14
Variation-Tolerant Elastic Clock Scheme for Low-Voltage Operations
2021 · Sungju Ryu, Jongeun Koo, et al. · IEEE Journal of Solid-State Circuits · 12
A 44.1TOPS/W Precision-Scalable Accelerator for Quantized Neural Networks in 28nm CMOS
2020 · Sungju Ryu, Hyungjun Kim, et al. · Custom Integrated Circuits Conference · 10
Binaryware: A High-Performance Digital Hardware Accelerator for Binary Neural Networks
2023 · Sungju Ryu, Youngtaek Oh, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 9
Area-Efficient Transposable 6T SRAM for Fast Online Learning in Neuromorphic Processors
2019 · Jongeun Koo, Jinseok Kim, et al. · Custom Integrated Circuits Conference · 9
TRIO-TCAM: An Area and Energy-Efficient Triple-State-in-Cell Ternary Content-Addressable Memory Architecture
2024 · Thanh-Dat Nguyen, Sungju Ryu, et al. · IEEE Access · 5
RADiT: Redundancy-Aware Diffusion Transformer Acceleration Leveraging Timestep Similarity
2025 · Youngjun Park, Sangyeon Kim, et al. · ACM/IEEE Design Automation Conference (DAC) · 4
Mobileware: Distributed Architecture With Channel Stationary Dataflow for MobileNet Acceleration
2024 · Sungju Ryu, Jaeyong Jang, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 4
Area-efficient one-cycle correction scheme for timing errors in flip-flop based pipelines
2016 · Jongeun Koo, Eunwoo Song, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 3
SpecBoost: Accelerating Tiled Sparse Matrix Multiplication via Dataflow Speculation
2025 · Gwanghwi Seo, Sungju Ryu · IEEE Access · 2
Resource Analysis on FPGA for Functional Verification of Digital SRAM PIM
2024 · Sungju Ryu · JSTS Journal of Semiconductor Technology and Science · 2
Area-efficient AdderNet hardware accelerator with merged adder tree structure
2023 · Gwanghwi Seo, Sungju Ryu · IEICE Electronics Express · 2
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Area-efficient Transposable Crossbar Synapse Memory Using 6T SRAM Bit Cell for Fast Online Learning of Neuromorphic Processors
2020 · Jongeun Koo, Jinseok Kim, et al. · JSTS Journal of Semiconductor Technology and Science · 2
Low design overhead timing error correction scheme for elastic clock methodology
2017 · Sungju Ryu, Jongeun Koo, et al. · International Symposium on Low Power Electronics and Design (ISLPED) · 2
Sparse-on-Dense: Area and Energy-Efficient Computing of Sparse Neural Networks on Dense Matrix Multiplication Accelerators
2026 · Yoon, Hyunsung, Ryu, Sungju, et al. · arXiv (Cornell University) · 1
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E-Flash: Energy-Efficient DNN Mapping on NAND Flash Memory with State-Switching Algorithm
2025 · Gisan Ji, Sanghun Shin, et al. · International Symposium on Low Power Electronics and Design (ISLPED) · 1
High-performance Sparsity-aware NPU with Reconfigurable Comparator-multiplier Architecture
2024 · Sungju Ryu, Jae-Joon Kim · JSTS Journal of Semiconductor Technology and Science · 1
Review and Analysis of Variable Bit-precision MAC Microarchitectures for Energy-efficient AI Computation
2022 · Sungju Ryu · JSTS Journal of Semiconductor Technology and Science · 1
SPRITE: Sparsity-Aware Neural Processing Unit with Constant Probability of Index-Matching
2021 · Sungju Ryu, Youngtaek Oh, et al. · Design, Automation, and Test in Europe · 1
Works count: 42
Citation count: 295
H-index: 9
I10-index: 9
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