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Nagendra Krishnapura
Observed name:
N. Krishnapura
Institution:
Indian Institute of Technology Madras
Observed institutions:
Indian Institute of Technology Madras,
Texas Instruments (India),
Alcatel-Lucent (France),
Indian Institute of Technology Delhi,
Columbia University
ORCID:
0000-0002-8429-8910
Observed ORCID:
0000-0002-8429-8910
OpenAlex ID:
A5080522900
A Power Optimized Continuous-Time $\Delta \Sigma $ ADC for Audio Applications
2008
·
Shanthi Pavan
, Nagendra Krishnapura
, et al.
·
IEEE Journal of Solid-State Circuits
·
136
Analysis and Design of a Discrete-Time Delta-Sigma Modulator Using a Cascoded Floating-Inverter-Based Dynamic Amplifier
2022
·
R. S. Ashwin Kumar
, Nagendra Krishnapura
, et al.
·
IEEE Journal of Solid-State Circuits
·
114
A 2-GHz Bandwidth, 0.25–1.7 ns True-Time-Delay Element Using a Variable-Order All-Pass Filter Architecture in 0.13 $\mu$ m CMOS
2017
·
Imon Mondal
, Nagendra Krishnapura
·
IEEE Journal of Solid-State Circuits
·
93
26.3 A 25-to-38GHz, 195dB FoMT LC QVCO in 65nm LP CMOS Using a 4-Port Dual-Mode Resonator for 5G Radios
2019
·
Abhishek Bhat
, Nagendra Krishnapura
·
Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
·
78
A 5.3-GHz programmable divider for HiPerLAN in 0.25-/spl mu/m CMOS
2000
·
N. Krishnapura
, P.R. Kinget
·
IEEE Journal of Solid-State Circuits
·
73
Hand Talk-Implementation of a Gesture Recognizing Glove
2013
·
Celestine Preetham
, Girish Ramakrishnan
, et al.
·
Texas Instruments India Educators' Conference (TIIEC)
·
63
A 5.3GHz programmable divider for HiPerLAN in 0.25µm CMOS
1999
·
Nagendra Krishnapura
, Peter R. Kinget
·
European Solid-State Circuits Conference (ESSCIRC)
·
56
Internally varying analog circuits minimize power dissipation
2003
·
Y. Tsividis
, N. Krishnapura
, et al.
·
IEEE Circuits and Devices Magazine
·
52
A 5Gb/s NRZ transceiver with adaptive equalization for backplane transmission
2005
·
N. Krishnapura
, M. Barazande-Pour
, et al.
·
Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
·
44
A 16 MHz BW 75 dB DR CT $\Delta\Sigma$ ADC Compensated for More Than One Cycle Excess Loop Delay
2012
·
Vikas Singh
, Nagendra Krishnapura
, et al.
·
IEEE Journal of Solid-State Circuits
·
42
Noise and power reduction in filters through the use of adjustable biasing
2001
·
N. Krishnapura
, Y.P. Tsividis
·
IEEE Journal of Solid-State Circuits
·
34
Compensating for Quantizer Delay in Excess of One Clock Cycle in Continuous-Time $\Delta\Sigma$ Modulators
2010
·
Vikas Singh
, Nagendra Krishnapura
, et al.
·
IEEE Transactions on Circuits & Systems II Express Briefs
·
23
25.4 A 500Mb/s 200pJ/b die-to-die bidirectional link with 24kV surge isolation and 50kV/µs CMR using resonant inductive coupling in 0.18µm CMOS
2017
·
Subhashish Mukherjee
, Anoop Narayan Bhat
, et al.
·
Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
·
21
A High-IIP3 Third-Order Elliptic Filter With Current-Efficient Feedforward-Compensated Opamps
2011
·
Nagendra Krishnapura
, Abhishek Agrawal
, et al.
·
IEEE Transactions on Circuits & Systems II Express Briefs
·
21
On the analysis of noise and interference in instantaneously companding signal processors
1998
·
L. Toth
, Y.P. Tsividis
, et al.
·
IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing
·
21
Multi-Channel Analog-to-Digital Conversion Techniques Using a Continuous-Time Delta-Sigma Modulator Without Reset
2020
·
R. S. Ashwin Kumar
, Nagendra Krishnapura
·
IEEE Transactions on Circuits and Systems I Regular Papers
·
20
On Pulse Position Modulation and Its Application to PLLs for Spur Reduction
2011
·
Chembiyan Thambidurai
, Nagendra Krishnapura
·
IEEE Transactions on Circuits and Systems I Regular Papers
·
20
Automatic Tuning of Time Constants in Continuous-Time Delta–Sigma Modulators
2007
·
Shanthi Pavan
, Nagendra Krishnapura
·
IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing
·
17
Low $1/f^{3}$ Phase Noise Quadrature LC VCOs
2018
·
Abhishek Bhat
, Nagendra Krishnapura
·
IEEE Transactions on Circuits and Systems I Regular Papers
·
16
Simplified technique for syllabic companding inlog-domain filters
2000
·
N. Krishnapura
, Y. Tsividis
, et al.
·
Electronics Letters
·
16
A 6 to 12-GHz Fractional-N Frequency Synthesizer With a Digital Technique to Counter Modulus-Dependent Feedback Divider Delays
2024
·
Aditya Narayanan
, Abhishek Bhat
, et al.
·
IEEE Journal of Solid-State Circuits
·
15
A 1.2 V 285μA analog front end chip for a digital hearing aid in 0.13 μm CMOS
2013
·
Amrith Sukumaran
, Kunal Karanjkar
, et al.
·
IEEE Asian Solid-State Circuits Conference (A-SSCC)
·
15
Syllabic-companding log domain filters
2001
·
D. Frey
, Y.P. Tsividis
, et al.
·
IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing
·
14
Reset-Free Memoryless Delta–Sigma Analog-to-Digital Conversion
2018
·
R. S. Ashwin Kumar
, Debasish Behera
, et al.
·
IEEE Transactions on Circuits and Systems I Regular Papers
·
13
A Flexible 18-Channel Multi-Hit Time-to-Digital Converter for Trigger-Based Data Acquisition Systems
2020
·
Chithra
, Nagendra Krishnapura
·
IEEE Transactions on Circuits and Systems I Regular Papers
·
12
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Works count:
107
Citation count:
1,275
H-index:
17
I10-index:
28
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