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D. R. Premachand

Observed names: D R Premachand, D.R Premachand, Premachand D R, Premachand D. R.
OpenAlex ID: A5080627053
Efficient 1-Bit Full Adder Implementation with Reduced MOSFET Count
2024 · D R Premachand, K M Srikantha · International Conference on Networks, Multimedia and Information Technology (NMITCON) · 2
Sector-Selective Hybrid Scheme Facilitating Hardware Supportability Over Image Compression
2020 · D. R. Premachand, U. Eranna · Advances in intelligent systems and computing · 2
Novel hybrid framework for image compression for supportive hardware design of boosting compression
2021 · Premachand D. R., U. Eranna · International Journal of Power Electronics and Drive Systems/International Journal of Electrical and Computer Engineering
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Design and Development of a Very Large Scale Integrated Circuit Architecture for a Digital Image Compression and Realization on Field Programmable Gate Array
2020 · Premachand D R, U. Eranna* · International Journal of Innovative Technology and Exploring Engineering
Design of Area Effective Full Adder Using Gate Diffusion Input Logic
2018 · D.R Premachand, U. Eranna, et al. · International Conference on Electrical, Electronics, Communication, Computer and Optimization Techniques (ICEECCOT)
Design and simulation of low drop out voltage using 180nm CMOS technology
2017 · D. R. Premachand, U. Eranna · International Conference on Electrical, Electronics, Communication, Computer and Optimization Techniques (ICEECCOT)
Works count: 6
Citation count: 4
H-index: 2
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