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Necati Uysal

Observed name: Uysal Necati
Observed institution: University of Central Florida
ORCID: 0000-0002-9543-3823
Observed ORCID: 0000-0002-9543-3823
OpenAlex ID: A5081266557
Handling Stuck-at-Fault Defects Using Matrix Transformation for Robust Inference of DNNs
2019 · Baogang Zhang, Necati Uysal, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 52
Handling stuck-at-faults in memristor crossbar arrays using matrix transformations
2019 · Baogang Zhang, Necati Uysal, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 43
XMAP: Programming Memristor Crossbars for Analog Matrix–Vector Multiplication: Toward High Precision Using Representable Matrices
2021 · Necati Uysal, Baogang Zhang, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 9
Computational Restructuring: Rethinking Image Compression Using Resistive Crossbar Arrays
2020 · Baogang Zhang, Necati Uysal, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 9
Computational Restructuring: Rethinking Image Processing using Memristor Crossbar Arrays
2020 · Baogang Zhang, Necati Uysal, et al. · Design, Automation, and Test in Europe · 6
Representable Matrices: Enabling High Accuracy Analog Computation for Inference of DNNs using Memristors
2020 · Baogang Zhang, Necati Uysal, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 5
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DP-MAP
2020 · Necati Uysal, Baogang Zhang, et al. · 4
Latency constraint guided buffer sizing and layer assignment for clock trees with useful skew
2019 · Necati Uysal, Wen-Hao Liu, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 4
OCV guided clock tree topology reconstruction
2018 · Necati Uysal, Rickard Ewetz · Asia and South Pacific Design Automation Conference (ASP-DAC) · 4
Redundant Neurons and Shared Redundant Synapses for Robust Memristor-based DNNs with Reduced Overhead
2020 · Baogang Zhang, Necati Uysal, et al. · ACM Great Lakes Symposium on VLSI (GLSVLSI) · 3
STAT
2019 · Baogang Zhang, Necati Uysal, et al. · ACM Great Lakes Symposium on VLSI (GLSVLSI) · 3
An OCV-Aware Clock Tree Synthesis Methodology
2021 · Necati Uysal, Rickard Ewetz · International Conference on Computer Aided Design · 2
OCV guided clock tree topology reconstruction
2018 · Necati Uysal, Rickard Ewetz · Asia and South Pacific Design Automation Conference (ASP-DAC) · 2
Synthesis of Clock Networks with a Mode-Reconfigurable Topology
2022 · Necati Uysal, Rickard Ewetz · ACM Transactions on Design Automation of Electronic Systems · 1
Synthesis of Clock Networks with a Mode Reconfigurable Topology and No Short Circuit Current
2020 · Necati Uysal, Juan Ariel Cabrera, et al. · International Symposium on Physical Design · 1
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有用なスキューを持つクロックツリーのための待ち時間制約誘導バッファサイジングと層割当【jst・京大機械翻訳】
2019 · Uysal Necati, Liu Wenhao, et al. · ACM Proceedings
Works count: 16
Citation count: 148
H-index: 5
I10-index: 2
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