Author

Pierre Maillard

Observed names: Maillard, Pierre, P Maillard, P. Maillard

Observed institutions: Tokyo Institute of Technology, University of Electronic Science and Technology of China, Maharishi Markandeshwar University, Mullana, Vanderbilt University, Xilinx (United States), Xilinx (Ireland), Advanced Micro Devices (United States), University of Haifa

ORCID: 0000-0002-0919-9592

Observed ORCID: 0000-0002-0919-9592

OpenAlex ID: A5081461796

Single-Event Latch-Up: Increased Sensitivity From Planar to FinFET

2017 · James Karp, Michael J. Hart, et al. · IEEE Transactions on Nuclear Science · 47

Neutron, 64 MeV Proton, Thermal Neutron and Alpha Single-Event Upset Characterization of Xilinx 20nm UltraScale Kintex FPGA

2015 · Pierre Maillard, Michael Hart, et al. · IEEE Radiation Effects Data Workshop (REDW) · 36

Radiation-Tolerant Deep Learning Processor Unit (DPU)-Based Platform Using Xilinx 20-nm Kintex UltraScale FPGA

2022 · Pierre Maillard, Yanran P. Chen, et al. · IEEE Transactions on Nuclear Science · 28

An RHBD Technique to Mitigate Missing Pulses in Delay Locked Loops

2010 · Pierre Maillard, W. Timothy Holman, et al. · IEEE Transactions on Nuclear Science · 28

Single-Event Transient Induced Harmonic Errors in Digitally Controlled Ring Oscillators

2014 · Y. P. Chen, T. D. Loveless, et al. · IEEE Transactions on Nuclear Science · 22

Neutron, 64 MeV Proton & Alpha Single-event Characterization of Xilinx 16nm FinFET Zynq® UltraScale+™ MPSoC

2017 · Pierre Maillard, Michael Hart, et al. · IEEE Radiation Effects Data Workshop (REDW) · 21

Single-Event Evaluation of Xilinx 16nm UltraScale+™ Single Event Mitigation IP

2018 · Pierre Maillard, Michael J. Hart, et al. · IEEE Nuclear and Space Radiation Effects Conference (NSREC) · 18

The impact of device width on the variability of post-irradiation leakage currents in 90 and 65 nm CMOS technologies

2012 · Nadia Rezzak, Pierre Maillard, et al. · Microelectronics Reliability · 18

Single Event Latchup (SEL) and Single Event Upset (SEU) Evaluation of Xilinx 7nm Versal™ ACAP programmable logic (PL)

2021 · Pierre Maillard, Yanran P. Chen, et al. · IEEE Nuclear and Space Radiation Effects Conference (NSREC) · 14

Evaluation of ISO 26262 and IEC 61508 metrics for transient faults of a multi-processor system-on-chip through radiation testing

2020 · Oscar Ballan, Pierre Maillard, et al. · Microelectronics Reliability · 14

Test Methodology & Neutron Characterization of Xilinx 16nm Zynq® UltraScale+™ Multi-Processor System-on-Chip (MPSoC)

2018 · Pierre Maillard, Jue Arver, et al. · IEEE Nuclear and Space Radiation Effects Conference (NSREC) · 13

A New Error Correction Circuit for Delay Locked Loops

2013 · Pierre Maillard, W. Timothy Holman, et al. · IEEE Transactions on Nuclear Science · 11

Impact of Temperature and Vcc Variation on 20nm Kintex UltraScale FPGAs Neutron Soft Error Rate

2015 · Pierre Maillard, Michael Hart, et al. · IEEE Radiation Effects Data Workshop (REDW) · 10

Single Event Transient and ELDRS Characterization Test Results for LM4050QML 2.5V Precision Reference

2010 · Kirby Kruckmeyer, Elisa Morozumi, et al. · IEEE Radiation Effects Data Workshop (REDW) · 10

Total Ionizing Dose and Single-Events characterization of Xilinx 20nm Kintex UltraScale™

2019 · Pierre Maillard, Jeff Barton, et al. · European Conference on Radiation and Its Effects on Components and Systems · 9

Neutron and 64MeV Proton Characterization of Xilinx 7nm Versal TM Multicore Scalar Processing System (PS)

2022 · Pierre Maillard, Y. Paula Chen, et al. · IEEE Radiation Effects Data Workshop (REDW) · 8

Single-Event Upsets Characterization & Evaluation of Xilinx UltraScale™ Soft Error Mitigation (SEM IP) Tool

2016 · Pierre Maillard, Michael Hart, et al. · IEEE Radiation Effects Data Workshop (REDW) · 8

64MeV Proton single-event evaluation of Xilinx Single Event Mitigation (XilSEM) firmware on 7nm Versal™ ACAP devices

2022 · Yanran Paula Chen, Pierre Maillard, et al. · IEEE Radiation Effects Data Workshop (REDW) · 7

64 MeV Proton Single-Event Upset Characterization of Customer Memory Interface Design on Xilinx XCKU040 FPGA

2017 · Yanran P. Chen, Pierre Maillard, et al. · IEEE Radiation Effects Data Workshop (REDW) · 7

7nm FinFET technology heavy ion SEL evaluation using Xilinx Versal as case study

2021 · Arnaud Dufour, Jérôme Carron, et al. · European Conference on Radiation and Its Effects on Components and Systems · 6

Single event transient modeling and mitigation techniques for mixed-signal delay locked loop (DLL) and clock circuits

2014 · Pierre Maillard · PhDT · 5

Radiation-hardened-by-design (RHBD) delay locked loops (DLLS): single event transient analysis, simulation, and hardening

2010 · Pierre Maillard · 5

Protons Evaluation of 7nm Versal™ AI Engine (AIE) Based Radiation Tolerant Platform for Deep Learning Applications

2024 · Pierre Maillard, Abhijitt Dhavlle, et al. · IEEE Radiation Effects Data Workshop (REDW) · 4

Heavy-Ion and Proton Evaluation of AMD 7nm Versal™ Multicore Scalar Processing System (PS)

2023 · Pierre Maillard, Yanran P. Chen, et al. · IEEE Radiation Effects Data Workshop (REDW) · 4

Competitive Quality and Innovation

2015 · Pierre Maillard · Wiley eBooks · 4

Works count: 54

Citation count: 371

H-index: 11

I10-index: 14