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Teresa Cervero

Observed names: Cervero, Teresa, T. Cervero, Teresa G. Cervero
ORCID: 0000-0001-7535-4821
Observed ORCID: 0000-0001-7535-4821
OpenAlex ID: A5082644289
A Scalable and Dynamically Reconfigurable FPGA-Based Embedded System for Real-Time Hyperspectral Unmixing
2014 · Teresa G. Cervero, Julian Caba, et al. · IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing · 19
Survey of reconfigurable architectures for multimedia applications
2009 · T. Cervero, S. López, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 10
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Accelerating SpMV on FPGAs Through Block-Row Compress: A Task-Based Approach
2023 · José Oliver, Carlos Álvarez, et al. · International Conference on Field Programmable Logic and Applications (FPL) · 9
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Makinote: An FPGA-Based HW/SW Platform for Pre-Silicon Emulation of RISC-V Designs
2024 · Elias Perdomo, Alexander Kropotov, et al. · 8
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Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs
2011 · A. Otero, E. De La Torre, et al. · International Conference on Field Programmable Logic and Applications (FPL) · 8
A Resource Manager for Dynamically Reconfigurable FPGA-Based Embedded Systems
2013 · T. Cervero, J. Dondo, et al. · Euromicro Conference on Digital System Design (DSD) · 7
Scalable Models for Autonomous Self-Assembled Reconfigurable Systems
2011 · T. Cervero, S. Lopez, et al. · International Conference on ReConFigurable Computing and FPGAs (ReConFig) · 7
STRATUM project: AI-based point of care computing for neurosurgical 3D decision support tools
2025 · Himar Fabelo, Raquel Leon, et al. · Microprocessors and Microsystems · 5
3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project
2024 · Himar Fabelo, Raquel Leon, et al. · Euromicro Conference on Digital System Design (DSD) · 4
Scalable architectures for real-time hyperspectral unmixing
2014 · T. Cervero, S. López, et al. · Microelectronics Journal · 4
A scalable H.264/AVC deblocking filter architecture
2013 · T. Cervero, A. Otero, et al. · Journal of Real-Time Image Processing · 4
A Modular-Based Assembly Framework for Autonomous Reconfigurable Systems
2012 · Tannous Frangieh, Richard Stroop, et al. · Lecture notes in computer science · 4
Memory Sandbox: A Versatile Tool for Analyzing and Optimizing HBM Performance in FPGA
2024 · Elias Perdomo, Xavier Martorell, et al. · International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD) · 3
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Optimizations for Very Long and Sparse Vector Operations on a RISC-V VPU: A Work-in-Progress
2023 · Gopinath Mahale, Tejas Limbasiya, et al. · Lecture notes in computer science · 3
A novel scalable Deblocking Filter architecture for H.264/AVC and SVC video codecs
2011 · T. Cervero, A. Otero, et al. · IEEE International Conference on Multimedia and Expo (ICME) · 3
Scalable 2D architecture for H.264 SVC deblocking filter with reconfiguration capabilities for on-demand adaptation
2011 · T. Cervero, A. Otero, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 3
Ethernet Emulation over PCIe for RISC-V Software Development Vehicles
2023 · David Castells-Rufas, Xavier Martorell, et al. · Conference on Design of Circuits and Integrated Systems · 2
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b8c: SpMV accelerator implementation leveraging high memory bandwidth
2023 · José Oliver, Carlos Álvarez, et al. · IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) · 2
Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC and SVC Video Codecs
2012 · Andrés Otero, Teresa Cervero, et al. · Springer eBooks · 2
The remarkable evolution of microelectronics and microprocessors: Devices that changed the world
2026 · Teresa Cervero, Adrià Armejach, et al. · Microprocessors and Microsystems · 1
A hierarchical scheduling and management solution for dynamic reconfiguration in FPGA-based embedded systems
2013 · T. Cervero, A. Gómez, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1
Verification and Validation (V&V)-in-Loop for RISC-V Chip Design: The Holistic Vision of BZL
2026 · Sajjad Ahmed, Alexander Kropotov, et al. · ACM International Conference on Computing Frontiers: Workshops and Special Sessions (CF Companion)
Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL
2026 · Ahmed, Sajjad, Kropotov, Alexander, et al. · arXiv (Cornell University)
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Multi Partner Project: STRATUM, co-creation protocol and advanced smart GUI for a 3D neurosurgery supporting tool
2026 · Emanuele Torti, Himar Fabelo, et al. · Design, Automation, and Test in Europe
Memory Sandbox 2.0: A Framework for Enabling HBM2e vs HBM2 Performance and Telemetry Analysis on Xilinx FPGAs
2025 · Elias Perdomo, Joan Teruel, et al. · International Symposium on Memory Systems (MEMSYS)
Works count: 28
Citation count: 109
H-index: 7
I10-index: 2
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