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Chandan Karfa

Observed names: C. Karfa, Chandan  Karfa, Karfa, Chandan
ORCID: 0000-0002-3835-4184
Observed ORCID: 0000-0002-3835-4184
OpenAlex ID: A5083752855
An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis
2008 · Chandan Karfa, D. Sarkar, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 68
Verification of Code Motion Techniques Using Value Propagation
2014 · Kunal Banerjee, Chandan Karfa, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 55
Formal verification of code motion techniques using data-flow-driven equivalence checking
2012 · Chandan Karfa, Chittaranjan Mandal, et al. · ACM Transactions on Design Automation of Electronic Systems · 42
ChIRAAG: ChatGPT Informed Rapid and Automated Assertion Generation
2024 · Bhabesh Mali, Karthik Maddala, et al. · IEEE Computer Society Annual Symposium on VLSI · 40
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A Formal Verification Method of Scheduling in High-level Synthesis
2006 · C. Karfa, C. Mandal, et al. · International Symposium on Quality Electronic Design (ISQED) · 37
Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking
2020 · Tan, Benjamin, Karri, Ramesh, et al. · arXiv (Cornell University) · 33
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HMDS: A Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems
2021 · Debabrata Senapati, Arnab Sarkar, et al. · ACM Transactions on Embedded Computing Systems · 29
Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits
2010 · Chandan Karfa, Dipankar Sarkar, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 29
Is Register Transfer Level Locking Secure?
2020 · Chandan Karfa, Ramanuj Chouksey, et al. · Design, Automation, and Test in Europe · 28
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LAAG-RV: LLM Assisted Assertion Generation for RTL Design Verification
2024 · Karthik Maddala, Bhabesh Mali, et al. · IEEE International Test Conference India (ITC India) · 26
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Energy-Aware Real-Time Scheduling of Multiple Periodic DAGs on Heterogeneous Systems
2022 · Debabrata Senapati, Arnab Sarkar, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 25
FastSim: A Fast Simulation Framework for High-Level Synthesis
2021 · Mohammed Abderehman, Jayprakash Patidar, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 22
Verification of Loop and Arithmetic Transformations of Array-Intensive Behaviors
2013 · Chandan Karfa, Kunal Banerjee, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 22
Verification of Scheduling of Conditional Behaviors in High-Level Synthesis
2020 · Ramanuj Chouksey, Chandan Karfa · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 20
BLAST: Belling the Black-Hat High-Level Synthesis Tool
2022 · Mohammed Abderehman, Rupak Gupta, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 16
Formal Modeling of Network-on-Chip Using CFSM and its Application in Detecting Deadlock
2020 · Surajit Das, Chandan Karfa, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 16
PRESTO: A Penalty-Aware Real-Time Scheduler for Task Graphs on Heterogeneous Platforms
2021 · Debabrata Senapati, Arnab Sarkar, et al. · IEEE Transactions on Computers · 14
A Value Propagation Based Equivalence Checking Method for Verification of Code Motion Techniques
2012 · Kunal Banerjee, Chandan Karfa, et al. · International Symposium on Electronic System Design · 12
ImageSpec: Efficient High-Level Synthesis of Image Processing Applications
2022 · Abdul Khader Thalakkattu Moosa, Nilotpola Sarma, et al. · Euromicro Conference on Digital System Design (DSD) · 10
Translation Validation of Code Motion Transformations Involving Loops
2018 · Ramanuj Chouksey, Chandan Karfa, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 10
TMDS: Temperature-aware Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems
2023 · Debabrata Senapati, Kousik Rajesh, et al. · ACM Transactions on Design Automation of Electronic Systems · 9
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HOST: HLS Obfuscations against SMT ATtack
2021 · Chandan Karfa, TM Abdul Khader, et al. · Design, Automation, and Test in Europe · 9
Translation Validation of Loop Invariant Code Optimizations Involving False Computations
2017 · Ramanuj Chouksey, Chandan Karfa, et al. · Communications in computer and information science · 9
Equivalence Checking of Array-Intensive Programs
2011 · C. Karfa, K. Banerjee, et al. · IEEE Computer Society Annual Symposium on VLSI · 9
SAT Based Partial Attack on Compound Logic Locking
2020 · Melbin John, Aadil Hoda, et al. · Asian Hardware Oriented Security and Trust Symposium (AsianHOST) · 8
Works count: 94
Citation count: 720
H-index: 16
I10-index: 20
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