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P. Muralidhar

Observed names: Dr. Muralidhar Pullakandam, Muralidhar P, Muralidhar P., Muralidhar Pullakandam, P MURALIDHAR, P Muralidhar, Pullakandam Muralidhar
ORCID: 0000-0002-3288-9989
Observed ORCID: 0000-0002-3288-9989
OpenAlex ID: A5085457323
Reconfigurable wireless sensor network node based on Nios core
2008 · P. Muralidhar, C.B. Rama Rao · International Conference on Wireless Communication and Sensor Network (WCSN) · 27
Weapon Object Detection Using Quantized YOLOv8
2023 · Muralidhar Pullakandam, Keshav Loya, et al. · International Conference on Energy, Power and Environment (ICEPE) · 20
A high-speed reusable quantized hardware accelerator design for CNN on constrained edge device
2023 · Rama Muni Reddy Yanamala, Muralidhar Pullakandam · Design Automation for Embedded Systems · 16
FPGA implementation of sine and cosine value generators using Cordic Algorithm for Satellite Attitude Determination and calculators
2010 · Shoaib Bhuria, P. Muralidhar · International Conference on Power, Control and Embedded Systems · 15
Convolutional Neural Network based Traffic-Sign Classifier Optimized for Edge Inference
2020 · B B Shabarinath, P. Muralidhar · IEEE Region 10 Conference (TENCON) · 14
FPGA-accelerated hybrid CNN-LSTM system for efficient EEG-based drowsiness recognition
2025 · Rama Muni Reddy Yanamala, Muralidhar Pullakandam · The Journal of Supercomputing · 12
An Effective Hybrid Deep Learning Model for Single-Channel EEG-Based Subject-Independent Drowsiness Recognition
2023 · Y. Rama Muni Reddy, P. Muralidhar, et al. · Brain Topography · 12
An Efficient Configurable Hardware Accelerator Design for CNN on Low Memory 32-Bit Edge Device
2022 · Rama Muni Reddy Yanamala, Muralidhar Pullakandam · IEEE International Symposium on Smart Electronic Systems (iSES) · 10
SoC-based real-time SVM classification with integrated training using HLS and PYNQ
2023 · Shabarinath B B, Muralidhar Pullakandam · Microprocessors and Microsystems · 9
Implementation of Reconfigurable Adaptive Filtering Algorithms
2009 · Srinivasa Chaitanya K., P. Muralidhar, et al. · International Conference on Signal Processing Systems (ICSPS) · 9
Empowering edge devices: FPGA‐based 16‐bit fixed‐point accelerator with SVD for CNN on 32‐bit memory‐limited systems
2024 · Rama Muni Reddy Yanamala, Muralidhar Pullakandam · International Journal of Circuit Theory and Applications · 7
Highly reliable XoR Feed Arbiter Physical Unclonable Function (XFAPUF) in 180 nm process for IoT security
2021 · Raveendra Podeti, Sreehari Rao Patri, et al. · Microprocessors and Microsystems · 7
Custom-IP for Gradient Descent Optimization based on Hardware/Software Co-design Paradigm
2020 · B B Shabarinath, P. Muralidhar · International Symposium on VLSI Design and Test (VDAT) · 6
Embedded Hardware-Efficient FPGA Architecture for SVM Learning and Inference
2025 · B. B. Shabarinath, Muralidhar Pullakandam · IEEE Access · 5
Customizable Dynamic Hand Gesture recognition System for Motor Impaired people using Siamese neural network
2019 · P. Muralidhar, Amartya Saha, et al. · International Conference of Artificial Intelligence and Information Technology (ICAIIT) · 5
Pipelined CORDIC Architecture Based DDFS Design and Implementation
2023 · Sandeep Kumar Verma, Muralidhar Pullakandam, et al. · IEEE India Conference · 4
Recursive Challenge Feed Arbiter Physical Unclonable Function (RC-FAPUF) In 180nm Process For Reliable Key Generation In IOT Security
2023 · Raveendra Podeti, Sreehari Rao Patri, et al. · IETE Technical Review · 4
Implementation of CORDIC based RAKE receiver architecture
2009 · K.S. Chaitanya, P. Muralidhar, et al. · IEEE International Conference on Computer Science and Information Technology · 4
Analysis of block matching motion estimation algorithms
2013 · P. Muralidhar, C. B. Rama Rao · International Conference on Computing, Communication and Networking Technologies (ICCCNT) · 3
Approximate Successive Cancellation Decoder for Polar Codes
2025 · Jali Nandini, Muralidhar Pullakandam, et al. · Defence Science Journal · 2
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Vision Transformer Implementation on Edge GPU (AGX Orin) for Image Classification
2024 · Muralidhar Pullakandam, Sharad Soni, et al. · International Conference on Pioneering Developments in Computer Science & Digital Technologies (IC2SDT) · 2
FPGA(ZCU104) Based Energy Efficient Accelerator for MobileNet-V1
2024 · Yanamala Rama Muni Reddy, Pullakandam Muralidhar, et al. · IEEE International Colloquium on Signal Processing & Its Applications (CSPA) · 2
Hardware/Software Co-Design for Traffic Sign Inference on Edge Using PYNQ
2024 · B. B. Shabarinath, P. Muralidhar · Lecture notes in electrical engineering · 2
Epileptic Seizure Inference using Kernalized SVM with integrated training on PYNQ Z2
2022 · B B Shabarinath, P Muralidhar · IEEE International Symposium on Smart Electronic Systems (iSES) · 2
Efficient successive cancellation decoder architecture for multi-kernel polar codes
2022 · Nandini Jali, Muralidhar P, et al. · IEEE International Symposium on Smart Electronic Systems (iSES) · 2
Works count: 64
Citation count: 220
H-index: 9
I10-index: 8
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