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K. Ragini

Observed names: DR.K. Ragini, Dr. K Ragini, Dr. K. Ragini, Dr.K. Ragini, Ragini, K., Ragini. K
ORCID: 0000-0002-0803-0496
Observed ORCID: 0000-0002-0803-0496
OpenAlex ID: A5085866186
A review on power optimization of linear feedback shift register (LFSR) for Low power built in self test (BIST)
2011 · T. Saraswathi, K. Ragini, et al. · International Conference on Electronics Computer Technology · 15
Design of a Novel High-Speed- and Energy-Efficient 32-Bit Carry-Skip Adder
2019 · B. Sanjana, K. Ragini · Lecture notes in networks and systems · 6
Variable Threshold MOSFET Approach (Through Dynamic Threshold MOSFET) For Universal Logic Gates
2010 · Ragini, K., Satyam, M., et al. · arXiv (Cornell University) · 4
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Ultra Low Power Digital Logic Circuits in Sub-threshold for Biomedical Applications
2009 · K. Ragini · 4
Design and Implementation of RNB multiplier Using NP Domino logic
2022 · Bhavana Majji, K. Ragini · International Conference on Recent Trends in Microelectronics, Automation, Computing and Communications Systems (ICMACC) · 2
Implementation of Unbiased Rounding for 64-Bit Floating Point Adder
2022 · Vani Dasu, K. Ragini · International Conference on Recent Trends in Microelectronics, Automation, Computing and Communications Systems (ICMACC) · 2
Design of a Highly Reliable and Reconfigurable Pulsed Latch Circuits
2019 · B. Keerthi, K. Ragini · Lecture notes in networks and systems · 2
Analysis of Serial-In Parallel-Out Finite Field Multiplier Using Various Domino Logic Styles
2023 · Bhavana Majji, K. Ragini · Advances in intelligent systems and computing · 1
VTMOS Circuits Realization through DTMOS Circuits
2013 · Dr.K. Ragini, M. Satyam, et al. · 1
VLSI Implementation of Power Efficient Flash ADC
2026 · K. Ragini, Krishna Kishore Gudimella, et al.
Design and Simulation of a High-Speed 16-Bit Successive Approximation Register ADC (SAR ADC) with Capacitive-DAC Implementation Using Verilog
2025 · M. Keerthana, K. Ragini, et al. · Lecture notes in electrical engineering
Variable Threshold MOSFET Approach (Through Dynamic Threshold MOSFET) For Universal Logic Gates
2025 · K. Ragini · SSRN Electronic Journal
AI and IOT Integrated Ambulance System
2023 · Dr. K. Ragini, K. Vaishnavi, et al. · International Journal for Research in Applied Science and Engineering Technology
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Design of High-Performance Core Micro-Architecture Based on 32- Bit RISC-V Instruction Set Architecture [ISA]
2023 · Dr. K. Ragini, Nidhi Jaiswal · International Journal for Research in Applied Science and Engineering Technology
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Artificial Neural Network Based Integrated Ambulance System
2023 · Dr. K. Ragini, Spoorthi G Kunch, et al. · International Journal for Research in Applied Science and Engineering Technology
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Implementation of 64-Bit Inexact Speculative Half Unit Biased Floating-Point Adder
2023 · Vani Dasu, K. Ragini · Advances in intelligent systems and computing
Design of 32x32 Reversible Unsigned Multiplier Using Dadda Tree Algorithm
2022 · Veena Durgam, Dr. K Ragini · ECS Transactions
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Design of high performance approximate redundant binary multiplier using 4:2 & 5:2 compressors
2021 · Sunkara Yuha Sridevi, K. Ragini, et al. · AIP conference proceedings
Design of a New Subthreshold-Level Shifter Using Self-controlled Current Limiter
2018 · Sheereen Sulthana, K. Ragini · Lecture notes in networks and systems
Design and Power Optimization of Schmitt triggers using Finfet Technology
2016 · Pushpam Kolusu, DR.K. Ragini · IOSR Journal of VLSI and Signal processing
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The High performance Multiplexer based Adder Circuits
2015 · Iosr Journals, Dr. K. Ragini · Figshare
Sub Threshold Shift Register Design Using Variable Threshold MOSFET Approach
2014 · Ragini. K, Dr. Satyam M, et al. · IOSR Journal of VLSI and Signal processing
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Vtmos-a new logic family for low power digital circuits
2012 · K. Ragini · INFLIBNET
Variable Threshold Mosfet Approch (Through Dynamic Threshold Mosfet) For Universal Logic Gates
2011 · K. Ragini, M. Satyam, et al. · Zenodo (CERN European Organization for Nuclear Research)
Works count: 26
Citation count: 37
H-index: 4
I10-index: 1
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