Get started
Author

Nivedita Shrivastava

Observed name: Shrivastava, Nivedita
ORCID: 0000-0001-8378-3634
Observed ORCID: 0000-0001-8378-3634
OpenAlex ID: A5086378743
Securator: A Fast and Secure Neural Processing Unit
2023 · Nivedita Shrivastava, Smruti Ranjan Sarangi · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · 20
PDF
A survey of hardware architectures for generative adversarial networks
2021 · Nivedita Shrivastava, Muhammad Abdullah Hanif, et al. · Journal of Systems Architecture · 19
Toward an Optimal Countermeasure for Cache Side-Channel Attacks
2022 · Nivedita Shrivastava, Smruti R. Sarangi · IEEE Embedded Systems Letters · 9
FPGA Implementation of RECTANGLE Block Cipher Architectures
2019 · Nivedita Shrivastava, Bibhudendra Acharya · International Journal of Innovative Technology and Exploring Engineering · 8
PC-ILP: A Fast and Intuitive Method to Place Electric Vehicle Charging Stations in Smart Cities
2023 · Mehul Bose, Bivas Ranjan Dutta, et al. · Smart Cities · 7
Efficient hardware implementations of QTL cipher for RFID applications
2020 · Bibhudendra Acharya, Pulkit Singh, et al. · International Journal of High Performance Systems Architecture · 7
VLSI Implementation of ESF and QTL Lightweight Ciphers
2020 · Nivedita Shrivastava, Bibhudendra Acharya, et al. · Lecture notes in electrical engineering · 3
SecScale : A Scalable and Secure Trusted Execution Environment for Servers
2025 · Ani Sunny, Nivedita Shrivastava, et al. · Journal of Systems Architecture · 2
PDF
PredStereo: An Accurate Real-time Stereo Vision System
2022 · Diksha Moolchandani, Nivedita Shrivastava, et al. · IEEE Winter Conference on Applications of Computer Vision · 2
A Theoretical Framework For Modeling Cache-based Side-Channel Attacks and Countermeasures
2025 · Nivedita Shrivastava, Smruti R. Sarangi · IEEE Computer Society Annual Symposium on VLSI · 1
A Novel Hardware Architecture for Rectangle Block Cipher
2020 · Nivedita Shrivastava, Pulkit Singh, et al. · Lecture notes in electrical engineering · 1
NeuroPlug: Plugging Side-Channel Leaks in NPUs using Space Filling Curves
2024 · Shrivastava, Nivedita, Sarangi, Smruti R. · arXiv (Cornell University)
PDF
SparseLock: Securing Neural Network Models in Deep Learning Accelerators
2023 · Shrivastava, Nivedita, Sarangi, Smruti R. · arXiv (Cornell University)
PDF
SecOComp: A Fast and Secure Simultaneous Compression and Encryption Scheme
2023 · Shrivastava, Nivedita, Sarangi, Smruti R. · arXiv (Cornell University)
PDF
SceDL: A Simultaneous Compression and Encryption Scheme for Deep Learning Models
2023 · Nivedita Shrivastava, smruti ranjan sarangi
SceDL: A Simultaneous Compression and Encryption Scheme for Deep Learning Models
2023 · Nivedita Shrivastava, smruti ranjan sarangi
PDF
Secocomp: A Fast and Secure Simultaneouscompression and Encryption Scheme
2023 · Nivedita Shrivastava, Smruti R. Sarangi · SSRN Electronic Journal
Lightweight Hardware Architecture for Eight-Sided Fortress Cipher in FPGA
2020 · Nivedita Shrivastava, Bibhudendra Acharya · Lecture notes in networks and systems
Works count: 18
Citation count: 79
H-index: 6
I10-index: 2
Year
Topic
Type