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Author

Uwe Dolinsky

Observed names: Dolinsky, Uwe, U. Dolinsky
Observed institution: Codeplay (United Kingdom)
ORCID: 0000-0002-1438-0142
Observed ORCID: 0000-0002-1438-0142
OpenAlex ID: A5086448315
PEPPHER: Efficient and Productive Usage of Hybrid Computing Systems
2011 · Siegfried Benkner, Sabri Pllana, et al. · IEEE Micro · 91
Offload – Automating Code Migration to Heterogeneous Multicore Systems
2010 · Pete Cooper, Uwe Dolinsky, et al. · Lecture notes in computer science · 47
Programmability and performance portability aspects of heterogeneous multi-/manycore systems
2012 · Christoph Keßler, Usman Dastgeer, et al. · 36
Programmability and performance portability aspects of heterogeneous multi-/manycore systems
2012 · C. Kessler, U. Dastgeer, et al. · Design, Automation, and Test in Europe · 26
The Development of a Genetic Programming Method for Kinematic Robot Calibration
2001 · Uwe Dolinsky · 10
Improving performance of SYCL applications on CPU architectures using LLVM-directed compilation flow
2022 · Pietro Ghiglio, Uwe Dolinsky, et al. · 8
Automatic Offloading of C++ for the Cell BE Processor: A Case Study Using Offload
2010 · Alastair F Donaldson, Uwe Dolinsky, et al. · ... International Conference on Complex, Intelligent and Software Intensive Systems · 7
Programming Heterogeneous Multicore Systems Using Threading Building Blocks
2011 · George Russell, Paul Keir, et al. · Lecture notes in computer science · 4
FPL Demo: A Learning-Based Motion Artefact Detector for Heterogeneous Platforms
2023 · Yunyi Zhao, Yunjia Xia, et al. · International Conference on Field Programmable Logic and Applications (FPL) · 2
TensorFlow Acceleration on ARM Hikey Board
2018 · Mehdi Goli, Luke Iwanski, et al. · International Workshop on OpenCL · 2
Building a Reusable and Extensible Automatic Compiler Infrastructure for Reconfigurable Devices
2023 · Zhenya Zang, Uwe Dolinsky, et al. · International Conference on Field Programmable Logic and Applications (FPL) · 1
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Improving performance of SYCL applications on CPU architectures using LLVM‐directed compilation flow
2023 · Pietro Ghiglio, Uwe Dolinsky, et al. · Concurrency and Computation Practice and Experience · 1
A C++ Programming Model for Heterogeneous System Architecture
2016 · Ralph Potter, Russell Bradford, et al. · Lecture notes in computer science · 1
The impact of diverse memory architectures on multicore consumer software
2011 · George Russel, Colin Riley, et al. · Workshop on Memory System Performance and Correctness · 1
A Novel Optimization Framework for fNIRS: Enhancing Brain Image Reconstruction for Neurorehabilitation
2025 · Yunyi Zhao, Uwe Dolinsky, et al. · IEEE Transactions on Neural Systems and Rehabilitation Engineering
Edge Acceleration for Machine Learning-based Motion Artifact Detection on fNIRS Dataset
2023 · Yunyi Zhao, Yunjia Xia, et al. · International Workshop on OpenCL
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Accelerating Simulink/Matlab projects with SYCL
2023 · Uwe Dolinsky · International Workshop on OpenCL
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OpenCL Acceleration for TensorFlow
2018 · Mehdi Goli, Luke Iwanski, et al.
Works count: 20
Citation count: 237
H-index: 7
I10-index: 5
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