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Mian Lou

Research and implementation of SEC-DED Hamming code algorithm
2013 · Yuanyuan Cui, Mian Lou, et al. · IEEE Region 10 Conference (TENCON) · 16
DAGNN-RE: Directed acyclic graph neural network for functional reverse engineering of gate-level netlist
2024 · Zongtai Li, Liang Yang, et al. · Integration · 7
SRAM-based in-memory-computing for AI edge devices
2022 · Weidong Xu, Mian Lou, et al. · International Conference on Electronics and Communication, Network and Computer Technology (ECNCT) · 4
FSMformer: An efficient direction-aware graph transformer for state register detection of gate-level netlist
2026 · Zongtai Li, Liang Yang, et al. · Integration · 3
An 8T and 10T static random access memory with bit-serial operations for in-memory computing
2023 · Weidong Xu, Mian Lou, et al. · Research Square · 2
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An energy-efficient two-level cache architecture for chip multiprocessors
2014 · Mian Lou, Longsheng Wu, et al. · International Conference on Computing, Communication and Networking Technologies (ICCCNT) · 2
Dynamic, Tagless Cache Coherence Architecture in Chip Multiprocessor
2014 · Mian Lou, Jianqing Xiao · Advances in intelligent systems and computing · 2
An Energy-Efficient Dual-Level Cache Architecture for Chip Multiprocessors
2015 · Mian Lou, Longsheng Wu, et al. · Lecture notes in electrical engineering · 1
A fault-tolerant SDRAM controller based on a dynamically reconfigurable shift register chain
2014 · Mian Lou, Yuanyuan Cui, et al. · IEEE International Conference on Progress in Informatics and Computing · 1
Implementing fast recovery for register alias table in out-of-order processors
2013 · Jianqing Xiao, Mian Lou, et al. · International Symposium on Instrumentation and Measurement, Sensor Network and Automation · 1
Dataset Design for State Register Detection Tasks in Gate-Level Netlists
2026 · Zongtai Li, Ruohao Su, et al. · International Symposium on Semiconductor and Electronic Technology (ISSET)
Dataset Design for Sub-circuit Identification Task in Gate-Level Netlists
2026 · Zongtai Li, Yiyang Liu, et al. · International Conference on Electronic Information Technology and Computer Engineering (EITCE)
GNN-Reliability: A Function-Aware Graph Neural Network for Reliability Prediction of Gate-Level Netlist
2026 · Zongta Li, Liang Yang, et al. · International Symposium of Electronics Design Automation (ISEDA)
Dataset Design for Reliability Prediction Tasks in Gate-Level Netlists
2026 · Zongtai Li, Zeyu Yang, et al. · International Conference on Electronics, Integrated Circuits and Communication Technology (EICCT)
Fast-Response and Low-Power Low-Dropout Regulator for In-Memory Computing
2024 · Weidong Xu, Mian Lou, et al. · Russian Microelectronics
Chisel言語に基づくRISC-Vプロセッサ設計技術【JST・京大機械翻訳】
2021 · Mian Lou, Haijin Zhang, et al. · 微电子学与计算机
A task-level superscalar microarchitecture for large scale chip multiprocessors
2014 · Jianqing Xiao, Pengwei Lv, et al. · IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)
A CAM fault-tolerant strategy for multiprocessor by using bloom filter and history lookup table
2013 · Mian Lou, Yuanyuan Cui, et al. · IEEE Region 10 Conference (TENCON)
Works count: 18
Citation count: 39
H-index: 3
I10-index: 1
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