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Rohit Dhiman

Observed name: R. Dhiman
ORCID: 0000-0001-9059-5885
Observed ORCID: 0000-0001-9059-5885
OpenAlex ID: A5086882226
SiGe/Si hetero nanotube JLFET for improved performance: proposal and investigation
2019 · A. Thakur, R. Dhiman · Electronics Letters · 30
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Proposal and Analysis of Mixed CNT Bundle for Sub-Threshold Interconnects
2019 · Ashish Singh, Rohit Dhiman · IEEE Transactions on Nanotechnology · 22
Nanoelectronics for Next-Generation Integrated Circuits
2022 · Rohit Dhiman · CRC Press eBooks · 17
A physics-based drain current model for Si1-xGex source/drain NT JLFET for enhanced hot carrier reliability with temperature measurement
2022 · Anchal Thakur, Rohit Dhiman · Microelectronics Journal · 17
Proposal and analysis of relative stability in mixed CNT bundle for sub-threshold interconnects
2021 · Ashish Singh, Rajeevan Chandel, et al. · Integration · 16
Impacts of core gate thickness and Ge content variation on the performance of Si1−xGex source/drain Si–nanotube JLFET
2021 · Anchal Thakur, Rohit Dhiman · Journal of Computational Electronics · 16
Variability Analysis of Stochastic Parameters on the Electrical Performance of On-Chip Current-Mode Interconnect System
2016 · Yash Agrawal, Rajeevan Chandel, et al. · IETE Journal of Research · 14
Compact Models and Performance Investigations for Subthreshold Interconnects
2014 · Rohit Dhiman, Rajeevan Chandel · Engergy systems in electrical engineering · 13
Comprehensive study of gate induced drain leakage in nanowire and nanotube junctionless FETs using Si1-xGex source/drain
2023 · Anchal Thakur, Rohit Dhiman · AEU - International Journal of Electronics and Communications · 11
Modeling and Analysis of Cu-Carbon Nanotube Composites for Sub-Threshold Interconnects
2022 · Ashish Singh, Brajesh Kumar Kaushik, et al. · IEEE Open Journal of Nanotechnology · 11
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Delay analysis of buffer inserted sub-threshold interconnects
2016 · Rohit Dhiman, Rajeevan Chandel · Analog Integrated Circuits and Signal Processing · 11
Dynamic Crosstalk Analysis in Coupled Interconnects for Ultra-Low Power Applications
2014 · Rohit Dhiman, Rajeevan Chandel · Circuits Systems and Signal Processing · 11
Proposal and analysis of carbon nanotube based differential multibit through glass vias
2022 · Ajay Kumar, Rajeevan Chandel, et al. · Microelectronics Journal · 10
High-performance Current Mode Receiver Design for On-chip VLSI Interconnects
2015 · Yash Agrawal, Rajeevan Chandel, et al. · Advances in intelligent systems and computing · 10
Temperature assessment of Si1-xGex source/drain heterojunction NT-JLFET for gate induced drain leakage ‒ A compact model
2021 · Anchal Thakur, Rohit Dhiman · Superlattices and Microstructures · 8
Design and Performance Analysis of SiGe Hetero Nanotube Junctionless FET
2019 · Anchal Thakur, Rohit Dhiman · IEEE Region 10 Conference (TENCON) · 8
Design and analysis of efficient multilevel receiver for current mode interconnect system
2014 · Yash Agrawal, Rajeevan Chandel, et al. · IEEE Students Conference on Electrical, Electronics and Computer Science · 8
Proposal and Analysis of Coaxial-Through-Glass Vias in 3-D Integration Using Multiresolution Time-Domain (MRTD) Technique
2024 · K. Madhu Kiran, Brajesh Kumar Kaushik, et al. · IEEE Transactions on Components Packaging and Manufacturing Technology · 7
Frequency response and transient analysis of through glass packaging vias using matrix-rational approximation (MRA) technique for three-dimensional ICs
2023 · Ajay Kumar, Rohit Dhiman · Microelectronics Journal · 7
Modeling and Analysis of Cu-CNT Composite Through Glass Vias in 3D ICs
2021 · Ajay Kumar, Rohit Dhiman · IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS) · 6
Crosstalk analysis of CMOS buffer driven interconnects for ultra-low power applications
2013 · Rohit Dhiman, Rajeevan Chandel · Journal of Computational Electronics · 6
Three-phased multi-scale residual-dense modified-U-Net architecture for deep image steganography
2025 · Suyash Sachdeva, Ujjwal Sharma, et al. · Computers & Electrical Engineering · 5
Signal Integrity Analysis of Tapered Through Packaging Multibit Glass Vias Using Exponential Matrix–Rational Approximation Technique
2025 · Ajay Kumar, Rohit Dhiman · IEEE Transactions on Components Packaging and Manufacturing Technology · 5
Brain-Computer Interfacing: Design of Virtual Keyboard
2021 · Palak Sood, Rohit Dhiman · International Conference on Computing, Communication and Networking Technologies (ICCCNT) · 5
Modeling of Mixed CNT Bundle for Sub-threshold Interconnects
2018 · Ashish Singh, Rohit Dhiman, et al. · IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS) · 5
Works count: 72
Citation count: 337
H-index: 11
I10-index: 14
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