Get started
Author

Xuerong Jia

Observed name: Jia Xuerong
ORCID: 0009-0001-6652-1859
Observed ORCID: 0009-0001-6652-1859
OpenAlex ID: A5087004940
A Stacked Embedded DRAM Array for LPDDR4/4X using Hybrid Bonding 3D Integration with 34GB/s/1Gb 0.88pJ/b Logic-to-Memory Interface
2020 · Bai Fujun, Jiang Xiping, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 44
A 135 GBps/Gbit 0.66 pJ/bit Stacked Embedded DRAM with Multilayer Arrays by Fine Pitch Hybrid Bonding and Mini-TSV
2023 · Song Wang, Bing Yu, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 31
A Low-Cost Reduced-Latency DRAM Architecture With Dynamic Reconfiguration of Row Decoder
2022 · Fujun Bai, Song Wang, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 13
A Cross-Process Signal Integrity Analysis (CPSIA) Method and Design Optimization for Wafer-on-Wafer Stacked DRAM
2024 · Xiping Jiang, Xuerong Jia, et al. · Micromachines · 8
PDF
A 3D Unified Analysis Method (3D-UAM) for Wafer-on-Wafer Stacked Near-Memory Structure
2025 · Song Wang, Yixin Guo, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 1
Works count: 7
Citation count: 100
H-index: 4
I10-index: 3
Year
Topic
Type