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Sujit Kumar Patel
Observed names:
Sujit K. PATEL,
Sujit K. Patel,
Sujit Kumar PATEL,
Sujit Patel
Institution:
Thapar Institute of Engineering & Technology
Observed institutions:
Thapar Institute of Engineering & Technology,
Jaypee University of Engineering and Technology, Guna
ORCID:
0000-0002-6160-1809
Observed ORCID:
0000-0002-6160-1809
OpenAlex ID:
A5087401305
Area–Delay–Power Efficient Carry-Select Adder
2014
·
Basant Kumar Mohanty
, Sujit Kumar Patel
·
IEEE Transactions on Circuits & Systems II Express Briefs
·
160
LoBA: A Leading One Bit Based Imprecise Multiplier for Efficient Image Processing
2020
·
Bharat Garg
, Sujit Kumar Patel
, et al.
·
Journal of Electronic Testing
·
39
Efficient VLSI Architecture for Decimation-in-Time Fast Fourier Transform of Real-Valued Data
2015
·
Pramod Kumar Meher
, Basant Kumar Mohanty
, et al.
·
IEEE Transactions on Circuits and Systems I Regular Papers
·
36
LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter
2015
·
Basant K. Mohanty
, Pramod Kumar Meher
, et al.
·
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
·
35
Reconfigurable Rounding Based Approximate Multiplier for Energy Efficient Multimedia Applications
2021
·
Bharat Garg
, Sujit Patel
·
Wireless Personal Communications
·
30
Reconfigurable Carry Look-Ahead Adder Trading Accuracy for Energy Efficiency
2020
·
Bharat Garg
, Sujit Kumar Patel
·
Journal of Signal Processing Systems
·
20
Area–delay and energy efficient multi‐operand binary tree adder
2020
·
Sujit Kumar Patel
, Subodh Kumar Singhal
·
IET Circuits Devices & Systems
·
13
Area-Delay Efficient and Low-Power Carry Skip Adder for High Performance Computing Systems
2019
·
Sujit Patel
, Bharat Garg
, et al.
·
IEEE International Symposium on Smart Electronic Systems (iSES)
·
13
Efficient very large‐scale integration architecture for variable length block least mean square adaptive filter
2015
·
Basant Kumar Mohanty
, Sujit Kumar Patel
·
IET Signal Processing
·
11
PDF
An Efficient Accuracy Reconfigurable CLA Adder Designs Using Complementary Logic
2020
·
Sujit Kumar Patel
, Bharat Garg
, et al.
·
Journal of Electronic Testing
·
10
Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder
2019
·
Subodh Kumar Singhal
, B. K. Mohanty
, et al.
·
Journal of Circuits Systems and Computers
·
9
A power and area efficient approximate carry skip adder for error resilient applications
2019
·
Sujit Kumar PATEL
, Bharat GARG
, et al.
·
TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES
·
8
A novel design of current differencing transconductance amplifier with high transconductance gain and enhanced bandwidth
2020
·
Shireesh Kumar RAI
, Rishikesh PANDEY
, et al.
·
TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES
·
7
Design of Frequency Sampling Rational Rate Polyphase FIR Converter
2023
·
K. Anjali Rao
, Abhishek Kumar
, et al.
·
IEEE Transactions on Circuits & Systems II Express Briefs
·
5
An area-delay efficient single-precision floating-point multiplier for VLSI systems
2023
·
Anuradha
, Sujit Kumar Patel
, et al.
·
Microprocessors and Microsystems
·
5
Design of low complexity parallel polyphase finite impulse response filter using coefficient symmetry
2022
·
Konudula Anjali Rao
, Abhishek Kumar
, et al.
·
IET Circuits Devices & Systems
·
4
PDF
An Automation Methodology for Amelioration of SpyGlassCDC Abstract View Generation Process
2021
·
Prabal Sharma
, Sujit Kumar Patel
·
International Conference for Convergence in Technology (I2CT)
·
2
Area-delay efficient Radix-4 8×8 Booth multiplier for DSP applications
2021
·
Subodh K. SINGHAL
, Sujit K. PATEL
, et al.
·
TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES
·
2
An efficient reconfigurable floating point multiplier design for signal processing applications
2026
·
Subodh Kumar Singhal
, Sujit Kumar Patel
, et al.
·
Review of Computer Engineering Research
PDF
A Novel High Performance DCT Architecture for Efficient Image Compression
2026
·
Rochika Garg
, Kashish Goyal
, et al.
·
Communications in computer and information science
Chua-oscillator-driven modified RC4 stream cipher and its FPGA prototyping for secure communication
2026
·
Navneet Sharma
, Pravindra Kumar
, et al.
·
Integration
An efficient method of modulo adder design for Digital Signal Processing applications
2025
·
Subodh Kumar Singhal
, Sumit Kumar
, et al.
·
MethodsX
Single Image Haze Removal Algorithm with Upgraded Transmission Map Model
2023
·
gaurav saxena
, Sujit Kumar Patel
, et al.
·
Research Square
PDF
Area and Power Efficient Modulo 2^n+1 Multiplier
2014
·
Journal Ijmer
, Pitambar Patra K.
, et al.
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Works count:
24
Citation count:
409
H-index:
10
I10-index:
10
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