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G. S. Visweswaran

Observed names: G .S Visweswaran, G S Visweswaran, G. S. VISWESWARAN, G. Visweswaran, G.S. Visweswaran, Gangaikondan S Visweswaran, Gangaikondan Subramani Visweswaran
OpenAlex ID: A5087664170
Digital fractional‐order differentiator and integrator models based on first‐order and higher order operators
2010 · Maneesha Gupta, Pragya Varshney, et al. · International Journal of Circuit Theory and Applications · 71
New Approach to Realize Fractional Power in $z$-Domain at Low Frequency
2011 · G S Visweswaran, P Varshney, et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 38
Quaternary logic circuits in 2- mu m CMOS technology
1990 · N.R. Shanbhag, D. Nagchoudhuri, et al. · IEEE Journal of Solid-State Circuits · 34
A 32 kb 0.35–1.2 V, 50 MHz–2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS
2017 · Anuj Grover, G. S. Visweswaran, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 16
An Equalizer With Controllable Transfer Function for 6-Gb/s HDMI and 5.4-Gb/s DisplayPort Receivers in 28-nm UTBB-FDSOI
2016 · Paramjeet Singh Sahni, Suresh Chandra Joshi, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 16
Implementation of switched capacitor fractional order differentiator (PDδ) circuit
2008 · Pragya Varshney, Maneesha Gupta, et al. · International Journal of Electronics · 13
Battery aware dynamic scheduling for periodic task graphs
2006 · Venkat Rao, Nicolas Navet, et al. · 13
Novel Digital Differentiator and Corresponding Fractional Order Differentiator Models
2008 · Maneesha Gupta, Pragya Varshney, et al. · International Conference on Signal Processing and Multimedia Applications · 11
Battery aware dynamic scheduling for periodic task graphs
2006 · V. Rao, N. Navet, et al. · IEEE International Parallel and Distributed Processing Symposium (IPDPS) · 11
Current transport in large-area Schottky barrier diodes
1979 · G.S. Visweswaran, R. Sharan · Proceedings of the IEEE · 10
A 0.5V VMIN 6T SRAM in 28nm UTBB FDSOI Technology Using Compensated WLUD Scheme with Zero Performance Loss
2016 · Ashish Kumar, G.S. Visweswaran, et al. · International Conference on VLSI Design · 8
Low Standby Power Capacitively Coupled Sense Amplifier for wide voltage range operation of dual rail SRAMs
2015 · Anuj Grover, Promod Kumar, et al. · IEEE International Conference on IC Design and Technology (ICICDT) · 8
Switched Capacitor Realizations of Fractional-Order Differentiators and Integrators Based on an Operator with Improved Performance
2011 · G. S. Visweswaran, Pradeep K. Varshney, et al. · 8
Texture Filter Memory – A Power-efficient and Scalable Texture Memory Architecture for Mobile Graphics Processors
2010 · B. V. N. Silpa, Anjul Patney, et al. · 8
First and higher order operator based fractional order differentiator and integrator models
2009 · P. Varshney, M. Gupta, et al. · IEEE Region 10 Conference (TENCON) · 8
A low-power ternary content addressable memory (TCAM) with segmented and non-segmented matchlines
2008 · M. Sultan, M. Siddiqui, et al. · IEEE Region 10 Conference (TENCON) · 8
Inclusion of thermal effects in the simulation of bipolar circuits using circuit level behavioral modeling
2004 · T.S. Shelar, G.S. Visweswaran · International Conference on VLSI Design · 8
A MOS transistor thermal sub-circuit for the SPICE circuit simulator
1998 · Saeiid Nooshabadi, G.S. Visweswaran, et al. · Microelectronics Journal · 6
Implementation of first and third order fractional order differentiators and integrators using switched capacitors
2011 · Pragya Varshney, Maneesha Gupta, et al. · India International Conference on Power Electronics (IICPE) · 5
Texture Filter Memory — a power-efficient and scalable texture memory architecture for mobile graphics processors
2008 · B. V. N. Silpa, Anjul Patney, et al. · 5
Spectral Density Driven Wavelet Representation of 2-D Images
2006 · Lalit K. Jiwani, S.D. Joshi, et al. · IEEE International Symposium on Signal Processing and Information Technology (ISSPIT) · 5
Micropipeline architecture for multiplier-less FIR filters
2002 · S. Nooshabadi, J.A. Montiel-Nelson, et al. · International Conference on VLSI Design · 5
A P1500 compliant programmable BistShell for embedded memories
2002 · S. Koranne, C. Wouters, et al. · Records of the IEEE International Workshop on Memory Technology, Design, and Testing · 5
A low power 256 KB SRAM design
1999 · B. Bhaumik, P. Pradhan, et al. · International Conference on VLSI Design · 4
Quasistatic analysis of a dynamic sense amplifier
1985 · G.S. Visweswaran, N.K. Jain, et al. · Electronics Letters · 4
Works count: 62
Citation count: 361
H-index: 10
I10-index: 10
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