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Jae-Won Nam

Observed names: Jae‐Won Nam, Nam Jae-Won, Nam Jaewon
ORCID: 0000-0003-0986-4107
Observed ORCID: 0000-0003-0986-4107
OpenAlex ID: A5087787392
A 12-Bit 1.6, 3.2, and 6.4 GS/s 4-b/Cycle Time-Interleaved SAR ADC With Dual Reference Shifting and Interpolation
2018 · Jae-Won Nam, Mohsen Hassanpourghadi, et al. · IEEE Journal of Solid-State Circuits · 79
A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique
2010 · Young-Kyun Cho, Young-Deuk Jeon, et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 52
Compact SRAM-Based PUF Chip Employing Body Voltage Control Technique
2022 · Jae-Won Nam, Ju-Hyeok Ahn, et al. · IEEE Access · 26
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A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash–SAR Architecture
2012 · Young-Deuk Jeon, Jae-Won Nam, et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 18
A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS
2016 · Jae-Won Nam, Mohsen Hassanpourghadi, et al. · Symposium on VLSI Circuits · 17
An Embedded Passive Gain Technique for Asynchronous SAR ADC Achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS
2016 · Jae-Won Nam, Mike Shuo-Wei Chen · IEEE Transactions on Circuits and Systems I Regular Papers · 16
A 9.15mW 0.22mm2 10b 204MS/s pipelined SAR ADC in 65nm CMOS
2010 · Young-Deuk Jeon, Young-Kyun Cho, et al. · Custom Integrated Circuits Conference · 13
A Reconfigurable SRAM CRP PUF with High Reliability and Randomness
2024 · Van Khanh Pham, Chi Trung Ngo, et al. · Electronics · 12
A Low-Power Class-C Voltage-Controlled Oscillator With Robust Start-Up and Compact High-Q Capacitor Array
2021 · Young-Kyun Cho, Jae-Won Nam, et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 12
Machine-Learning based Analog and Mixed-signal Circuit Design and Optimization
2021 · Jae-Won Nam, Youn Kyu Lee · International Conference on Information Networking · 10
A 95-MS/s 11-bit 1.36-mW asynchronous SAR ADC with embedded passive gain in 65nm CMOS
2013 · Jae-Won Nam, David Chiong, et al. · Custom Integrated Circuits Conference · 10
A Lightweight and High Yield Complementary Metal-Oxide Semiconductor True Random Number Generator with Lightweight Photon Post-Processing
2024 · Chi Trung Ngo, Hyun Woo Ko, et al. · Sensors · 9
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Solving Optimal Electric Vehicle Charger Deployment Problem
2024 · Seungmo Kim, Yeonho Jeong, et al. · Applied Sciences · 7
15.4–17 GHz, −187.4 dBc/Hz FoM VCO With Current Reused Coupled Oscillator and Improved Noise Circulation
2025 · Hapsah Aulia Azzahra, Muhammad Fakhri Mauludin, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 6
A 12.8-Gbaud ADC-Based Wireline Receiver With Embedded IIR Equalizer
2020 · Jae-Won Nam, Mike Shuo-Wei Chen · IEEE Journal of Solid-State Circuits · 6
Analysis of Quarter Method Applied ROM-Based DDFS Architecture
2023 · Jae-Yun Park, Su-Hyeon Kim, et al. · IEEE Access · 5
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Stochastic Cell- and Bit-Discard Technique to Improve Randomness of a TRNG
2022 · Jae-Won Nam, Jaewoo Kim, et al. · Electronics · 5
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Regression Model-Based AMS Circuit Optimization Technique Utilizing Parameterized Operating Condition
2022 · Jae-Won Nam, Young-Kyun Cho, et al. · Electronics · 5
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A 4.3 GS/s Time-Interleaved ΔΣ DAC With Temperature-Insensitive Bias and Harmonic Cancellation for Qubit Control
2024 · Jae-Yun Park, Jae-Won Nam · IEEE Transactions on Circuits & Systems II Express Briefs · 4
A 12-bit 100-MS/s pipelined ADC in 45-nm CMOS
2011 · Jae-Won Nam, Young-Deuk Jeon, et al. · International SoC Design Conference · 4
A 10-bit 30-MS/s successive approximation register analog-to-digital converter for low-power sub-sampling applications
2011 · Young-Kyun Cho, Young-Deuk Jeon, et al. · Microelectronics Journal · 4
A 1.2 V 12 b 60 MS/s CMOS Analog Front-End for Image Signal Processing Applications
2009 · Young-Deuk Jeon, Young-Kyun Cho, et al. · ETRI Journal · 4
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AI-Assisted Design Automation of Circular and Asymmetric Inductor in CMOS Technology
2024 · Jin-Won Hyun, Dana Kim, et al. · International SoC Design Conference · 3
A 12.8-Gbaud ADC-based NRZ/PAM4 Receiver with Embedded Tunable IIR Equalization Filter Achieving 2.43-pJ/b in 65nm CMOS
2019 · Jae-Won Nam, Mike Shuo-Wei Chen · Custom Integrated Circuits Conference · 3
A 2.85mW 0.12mm2 1.0V 11-bit 20-MS/s algorithmic ADC in 65nm CMOS
2009 · Jae-Won Nam, Young-Deuk Jeon, et al. · European Solid-State Circuits Conference (ESSCIRC) · 3
Works count: 42
Citation count: 345
H-index: 10
I10-index: 11
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