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Yung-Yu Lin

A Quadrature Bandpass Continuous-Time Delta-Sigma Modulator for a Tri-Mode GSM-EDGE/UMTS/DVB-T Receiver
2011 · Chen-Yen Ho, Wei-Shan Chan, et al. · IEEE Journal of Solid-State Circuits · 33
Enhancing construction project supply chains and performance evaluation methods: a case study of a bridge construction project
2010 · Nai-Hsin Pan, Yung-Yu Lin, et al. · Canadian Journal of Civil Engineering · 26
A 1-V 5-MHz Bandwidth 68.3-dB SNDR Continuous-Time Delta-Sigma Modulator With a Feedback-Assisted Quantizer
2017 · Chan-Hsiang Weng, Yung-Yu Lin, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 11
A 1.2V 2MHz BW 0.084mm2 CT ΔΣ ADC with −97.7dBc THD and 80dB DR using low-latency DEM
2009 · Sheng-Jui Huang, Yung-Yu Lin · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 11
The prediction system for data analysis of stock market by using Genetic Algorithm
2015 · Ching-Te Wang, Yung-Yu Lin · International Conference on Fuzzy Systems and Knowledge Discovery (FSKD) · 8
DLL-based clock recovery in a PRML channel
2005 · Ping Ying Wang, Hsueh-Wu Kao, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 8
Multi Period Performance Assessment Model for the Site Property Management
2014 · Yung-Yu Lin, Nai-Hsin Pan · International Journal of Strategic Property Management · 7
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Dual-mode Continuous-Time Quadrature Bandpass ΔΣ modulator with Pseudo-random Quadrature mismatch shaping algorithm for Low-IF receiver application
2010 · Chen-Yen Ho, Yung-Yu Lin, et al. · IEEE International Symposium on Circuits and Systems proceedings · 6
A TDC-Based Two-Step Quantizer With Swapper Technique for a Multibit Continuous-Time Delta–Sigma Modulator
2014 · Chen-Chien Lin, Chan-Hsiang Weng, et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 4
A quadrature bandpass continuous-time delta-sigma modulator for tri-mode GSM-EDGE/UMTS/DVB-T receivers, with power scaling technique
2010 · Chen-Yen Ho, Wei-Shan Chan, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 4
LMS-based digital background linearization technique for VCO-based delta-sigma ADC
2014 · Fu-Chien Huang, Shou-Chen Hsu, et al. · IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) · 3
Using hybrid simulated annealing algorithm in resource constrained project scheduling problem
2011 · Nai-Hsin Pan, Yung-Yu Lin · Journal of Statistics and Management Systems · 3
A Phase Locked Loop with a Mixed Mode Loop Filter for Clock/Data Recovery in Optical Disc Drives
2005 · Ping-Ying Wang, Hsiang Ji Hsieh, et al. · IEEE International Symposium on Circuits and Systems proceedings · 3
フィードバック支援量子化器を持つ1V,5MHz帯域幅/s68.3dB SNDR連続時間デルタシグマ変調器【Powered by NICT】
2017 · Weng Chan-Hsiang, Yung-Yu Lin, et al. · IEEE Transactions on Circuits and Systems I Regular Papers
A CMOS multi-format read/write soc for 7x blu-ray/16x DVD/56|CD
2005 · Jyh-Shin Pan, Pi-Hai Liu, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
31.2 DLL-Based Clock Recovery in a PRML Channel
2005 · Ping Ying Wang, Hsueh-Wu Kao, et al.
Works count: 16
Citation count: 127
H-index: 7
I10-index: 4
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