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Dipanjan Roy

Observed names: D. Roy, Roy Dipanjan
ORCID: 0000-0002-9875-4315
Observed ORCID: 0000-0002-9875-4315
OpenAlex ID: A5088900896
DSP design protection in CE through algorithmic transformation based structural obfuscation
2017 · Anirban Sengupta, Dipanjan Roy, et al. · IEEE Transactions on Consumer Electronics · 51
Triple-Phase Watermarking for Reusable IP Core Protection During Architecture Synthesis
2017 · Anirban Sengupta, Dipanjan Roy, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 44
Low-Cost Obfuscated JPEG CODEC IP Core for Secure CE Hardware
2018 · Anirban Sengupta, Dipanjan Roy, et al. · IEEE Transactions on Consumer Electronics · 29
Low Cost Functional Obfuscation of Reusable IP Cores Used in CE Hardware Through Robust Locking
2018 · Anirban Sengupta, Deepak Kachave, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 26
Protecting IP core during architectural synthesis using HLT‐based obfuscation
2017 · A. Sengupta, D. Roy · Electronics Letters · 22
Antipiracy-Aware IP Chipset Design for CE Devices: A Robust Watermarking Approach [Hardware Matters]
2017 · Anirban Sengupta, Dipanjan Roy · IEEE Consumer Electronics Magazine · 20
Low overhead symmetrical protection of reusable IP core using robust fingerprinting and watermarking during high level synthesis
2017 · Dipanjan Roy, Anirban Sengupta · Future Generation Computer Systems · 18
Enhancing Saliency of an Object Using Genetic Algorithm
2017 · Rajarshi Pal, Dipanjan Roy · Canadian Conference on Computer and Robot Vision · 10
Intellectual Property-Based Lossless Image Compression for Camera Systems [Hardware Matters]
2017 · Anirban Sengupta, Dipanjan Roy · IEEE Consumer Electronics Magazine · 8
Securing Hardware Accelerator during High-level Synthesis
2022 · Dipanjan Roy, Sabiya Jani Shaik, et al. · IEEE International Symposium on Hardware Oriented Security and Trust (HOST) · 5
Multilevel Watermark for Protecting DSP Kernel in CE Systems [Hardware Matters]
2019 · Dipanjan Roy, Anirban Sengupta · IEEE Consumer Electronics Magazine · 5
Reusable intellectual property core protection for both buyer and seller
2018 · Anirban Sengupta, Dipanjan Roy · International Conference on Consumer Electronics · 5
Mathematical Validation of HWT Based Lossless Image Compression
2017 · Anirban Sengupta, Dipanjan Roy · IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) · 5
PROTECTS: Progressive Rtl Obfuscation with ThrEshold Control Technique during architectural Synthesis
2024 · Sonam Sharma, Dipanjan Roy, et al. · ACM Transactions on Design Automation of Electronic Systems · 4
A Framework for Hardware Efficient Reusable IP Core for Grayscale Image CODEC
2017 · Anirban Sengupta, Dipanjan Roy, et al. · IEEE Access · 4
Automated low cost scheduling driven watermarking methodology for modern CAD high-level synthesis tools
2017 · Anirban Sengupta, Dipanjan Roy · Advances in Engineering Software · 4
Securing Hardware Accelerator Against Reverse Engineering Attack
2023 · Dipanjan Roy, Sabiya Jani Shaik, et al. · International Conference on Consumer Electronics · 3
Low cost optimized Trojan secured schedule at behavioral level for single & Nested loop control data flow graphs (Invited Paper)
2016 · Anirban Sengupta, Dipanjan Roy, et al. · Integration · 3
Low-Overhead Robust RTL Signature for DSP Core Protection: New Paradigm for Smart CE Design
2019 · Anirban Sengupta, Dipanjan Roy, et al. · International Conference on Consumer Electronics · 2
Signature-Free Watermark for Protecting Digital Signal Processing Cores Used in CE Devices [Hardware Matters]
2018 · Pallabi Sarkar, Dipanjan Roy, et al. · IEEE Consumer Electronics Magazine · 2
Obfuscated JPEG Image Decompression IP Core for Protecting Against Reverse Engineering [Hardware Matter]
2018 · Dipanjan Roy, Anirban Sengupta · IEEE Consumer Electronics Magazine · 2
Enhancing Saliency of a Target Object Through Color Modification of Every Object Using Genetic Algorithm
2018 · Dipanjan Roy, Rajarshi Pal · Advances in intelligent systems and computing · 1
Optimizing DSP Cores Using Design Transformation [Hardware Matters]
2018 · Dipanjan Roy, Pallabi Sarkar, et al. · IEEE Consumer Electronics Magazine · 1
Multi-phase watermark for IP core protection
2018 · Anirban Sengupta, Dipanjan Roy · International Conference on Consumer Electronics · 1
When Bigger Isn’t Stronger: Reassessing Security in Hardware Obfuscation
2026 · Sonam Sharma, Dipanjan Roy, et al. · International Conference on Consumer Electronics
Works count: 33
Citation count: 275
H-index: 8
I10-index: 8
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