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Chien-Chung Tsai
Observed names:
C.-C. Tsai,
Chien-chung Tsai
Institution:
Mentor Graphics (United States)
Observed institutions:
University of California, Santa Barbara,
Mentor Graphics (United States)
OpenAlex ID:
A5089543669
Optimal core wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm
2003
·
Yu Huang
, S.M. Reddy
, et al.
·
IEEE International Test Conference (ITC)
·
161
Resource allocation and test scheduling for concurrent test of core-based SOC design
2002
·
Yu Huang
, Wu-Tung Cheng
, et al.
·
Proceedings - Asian Test Symposium/Proceedings
·
144
Boolean functions classification via fixed polarity Reed-Muller forms
1997
·
Chien-Chung Tsai
, M. Marek-Sadowska
·
IEEE Transactions on Computers
·
67
Generalized Reed-Muller forms as a tool to detect symmetries
1996
·
Chien-Chung Tsai
, M. Marek-Sadowska
·
IEEE Transactions on Computers
·
63
Boolean matching using generalized Reed-Muller forms
1994
·
Chien-Chung Tsai
, Malgorzata Marek-Sadowska
·
ACM/IEEE Design Automation Conference (DAC)
·
44
PDF
Multilevel logic synthesis for arithmetic functions
1996
·
Chien-Chung Tsai
, M. Marek-Sadowska
·
ACM/IEEE Design Automation Conference (DAC)
·
36
On Concurrent Test of Core-Based SOC Design
2002
·
Yu Huang
, Wu-Tung Cheng
, et al.
·
Journal of Electronic Testing
·
33
On RTL scan design
2002
·
Yu Huang
, Chien-Chung Tsai
, et al.
·
IEEE International Test Conference (ITC)
·
25
Efficient minimization algorithms for fixed polarity AND/XOR canonical networks
2002
·
C.-C. Tsai
, M. Marek-Sadowska
·
ACM Great Lakes Symposium on VLSI (GLSVLSI)
·
17
Detecting symmetric variables in Boolean functions using generalized Reed-Muller forms
1994
·
Chien-Chung Tsai
, M. Marek-Sadowska
·
IEEE International Symposium on Circuits and Systems proceedings
·
16
Static pin mapping and SOC test scheduling for cores with multiple test sets
2004
·
Yu Huang
, Wu-Tung Cheng
, et al.
·
International Symposium on Quality Electronic Design (ISQED)
·
15
Minimisation of fixed-polarity AND/XOR canonical networks
1994
·
C.-C. Tsai
, M. Marek-Sadowska
·
IEE Proceedings - Computers and Digital Techniques
·
15
A novel combinational testability analysis by considering signal correlation
2002
·
Shih-Chieh Chang
, Shi-Sen Chang
, et al.
·
IEEE International Test Conference (ITC)
·
14
Constraint driven pin mapping for concurrent SOC testing
2003
·
Yu Huang
, Nilanjan Mukherjee
, et al.
·
Asia and South Pacific Design Automation Conference (ASP-DAC)
·
12
Synthesis of Scan Chains for Netlist Descriptions at RT-Level
2002
·
Yu Huang
, Chien-Chung Tsai
, et al.
·
Journal of Electronic Testing
·
10
Constraint-Driven Pin Mapping for Concurrent SOC Testing
2002
·
Yu Huang
, Yahya Zaidan
, et al.
·
9
Logic synthesis for testability
1996
·
Chien-Chung Tsai
, M. Marek-Sadowska
·
ACM Great Lakes Symposium on VLSI (GLSVLSI)
·
9
On Concurrent Test of Core-Based SOC Design
2002
·
Yu Huang
, Wu-Tung Cheng
, et al.
·
Frontiers in electronic testing
·
8
Effect of RTL coding style on testability
2002
·
Yu Huang
, Chien-Chung Tsai
, et al.
·
Custom Integrated Circuits Conference
·
1
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Works count:
19
Citation count:
699
H-index:
13
I10-index:
15
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