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D. Meganathan

Observed names: D Meganathan, MEGANATHAN D, Meganathan D, Meganathan D., Meganathan Deivasigamani, Meganathan, D.
ORCID: 0000-0003-3840-2155
Observed ORCID: 0000-0003-3840-2155
OpenAlex ID: A5090092563
Weed Detection in Farm Crops using Parallel Image Processing
2018 · S Umamaheswari, R Arjun, et al. · Conference on Information and Communication Technology (CICT) · 43
Q-Learning-Based Optimized Routing in Biomedical Wireless Sensor Networks
2016 · Jose Anand, J. Raja Paul Perinbam, et al. · IETE Journal of Research · 43
High performance VLSI adders
2015 · R. Suganya, D. Meganathan · International Conference on Signal Processing, Communication and Networking (ICSCN) · 28
Design of 8 bit Reconfigurable ALU Using Quantum Dot Cellular Automata
2018 · K. Pandiammal, D. Meganathan · IEEE Nanotechnology Materials and Devices Conference (NMDC) · 20
Efficient design of QCA based hybrid multiplier using clock zone based crossover
2019 · K. Pandiammal, D. Meganathan · Analog Integrated Circuits and Signal Processing · 16
A systematic design approach for low-power 10-bit 100 MS/s pipelined ADC
2009 · D. Meganathan, Amrith Sukumaran, et al. · Microelectronics Journal · 15
Design and implementation of in-situ human-elephant conflict management system
2019 · S. Jagannathan, V. Sathiesh Kumar, et al. · Journal of Intelligent & Fuzzy Systems · 11
An Improved ANFIS with Aid of ALO Technique for THD Minimization of Multilevel Inverters
2018 · Roy Francis, D. Meganathan · Journal of Circuits Systems and Computers · 11
A dual-mode cascaded H-bridge multilevel inverter for improving THD
2019 · Roy Francis, D. Meganathan · Electrical Engineering · 9
Diagnosis of Bearing Outer Race Faults Using a Low-Cost Non-Contact Method with Advanced Wavelet Transforms
2019 · Madhusudhana Reddy Barusu, Umamaheswari Sethurajan, et al. · Elektronika ir Elektrotechnika · 9
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Low‐cost SPLL‐based electrical faults identification for three‐phase squirrel cage induction motor using handheld Doppler radar signal analysis
2018 · Madhusudhana Reddy Barusu, Umamaheswari Sethurajan, et al. · IET Power Electronics · 9
Design and simulation of low power, high gain and high bandwidth recycling folded cascode OTA
2017 · T. V. Prasula, D. Meganathan · International Conference on Signal Processing, Communication and Networking (ICSCN) · 9
Low Jitter Adpll Based Clock Generator For High Speed Soc Applications
2008 · Moorthi, S., Meganathan, D., et al. · Zenodo (CERN European Organization for Nuclear Research) · 7
A Block Based Reversible Data Hiding Scheme for Digital Images Using Optimal Value Computation
2016 · D. R. Denslin Brabin, J. Raja Paul Perinbam, et al. · Wireless Personal Communications · 6
A systematic design of novel energy efficient 64-bit parallel-prefix adder
2020 · Jagadeeshkumar N, Meganathan D · International Journal of Electronics · 5
Noise reduction in underwater acoustic signals for tropical and subtropical coastal waters
2016 · Sumithra Ganapathi, Suresh Minakanoor Kumar, et al. · 5
Low jitter all digital phase locked loop based clock generator for high speed system on-chip applications
2009 · S. Moorthi, D. Meganathan, et al. · International Journal of Electronics · 5
Non-invasive vibration analysis with RDWT, UWB radar, and software PLL for open-phase and multiple bearing faults diagnosis in BLDC motor
2024 · P. Raja Shekhar, D. Meganathan · Electrical Engineering · 4
Watermark Visibility Adjustable RVW Scheme for JPEG Images
2020 · D. R. Denslin Brabin, J. Raja Paul Perinbam, et al. · Wireless Personal Communications · 4
QCA based FIR serial multiplier using cut-set algorithm
2017 · K. Pandiammal, D. Meganathan · IEEE International Conference on Nanotechnology (IEEE-NANO) · 4
A novel design of low power and high speed hybrid multiplier
2017 · N. Jagadeeshkumar, D. Meganathan · International Conference on Signal Processing, Communication and Networking (ICSCN) · 4
A low-jitter phase-locked loop architecture for clock generation in Analog to Digital Converters
2011 · S. Moorthi, D. Meganathan, et al. · IEEE Recent Advances in Intelligent Computational Systems · 3
High speed, low power 100 MS/s front end track-and-hold amplifier for ten-bit pipelined ADC
2009 · D. Meganathan, Raja Paul Perinbam, et al. · International Journal of High Performance Systems Architecture · 3
Design of Multiplexer Based 64-Bit SRAM Using QCA
2016 · K. Pandiammal, D. Meganathan · SSRN Electronic Journal · 2
Runtime buffer management to improve the performance in irregular Network-on-Chip architecture
2015 · UMAMAHESWARI S, MEGANATHAN D, et al. · Sadhana · 2
Works count: 40
Citation count: 287
H-index: 9
I10-index: 8
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