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Author

Yoshinobu Kaneda

Observed institution: Renesas Electronics (Japan)
ORCID: 0000-0002-2082-2023
Observed ORCID: 0000-0002-2082-2023
OpenAlex ID: A5090931576
15.8 A 22nm 10.8Mb Embedded STT-MRAM Macro Achieving over 200MHz Random-Read Access and a 10.4MB/s Write Throughput with an In-Field Programmable 0.3Mb MTJ-OTP for High-End MCUs
2024 · Tomoya Ogawa, Ken Matsubara, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 29
A 22nm 32Mb Embedded STT-MRAM Macro Achieving 5.9ns Random Read Access and 5.8MB/s Write Throughput at up to Tj of 150 °C
2022 · Takahiro Shimoi, Ken Matsubara, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 13
A 22-nm 32-Mb Embedded STT-MRAM Macro Achieving 5.9-ns Random Read Access and 7.4-MB/s Write Throughput at up to 150 °C
2023 · Takahiro Shimoi, Ken Matsubara, et al. · IEEE Journal of Solid-State Circuits · 12
A 40-nm Embedded SG-MONOS Flash Macro for High-End MCU Achieving 200-MHz Random Read Operation and 7.91-Mb/mm2 Density With Charge-Assisted Offset Cancellation Sense Amplifier
2022 · Masaya Nakano, Yoshinobu Kaneda, et al. · IEEE Journal of Solid-State Circuits · 10
A 65nm Silicon-on-Thin-Box (SOTB) Embedded 2T-MONOS Flash Achieving 0.22 pJ/bit Read Energy with 64 MHz Access for IoT Applications
2019 · Ken Matsubara, Tsutomu Nagasawa, et al. · Symposium on VLSI Circuits · 4
A 40nm Embedded SG-MONOS Flash Macro for High-end MCU Achieving 200MHz Random Read Operation and 7.91Mb/mm2 Density with Charge Assisted Offset Cancellation Sense Amplifier
2021 · Masaya Nakano, Yoshinobu Kaneda, et al. · IEEE Asian Solid-State Circuits Conference (A-SSCC) · 3
A 2T-MONOS Embedded Flash Macro With 65-nm SOTB Technology Achieving 0.15-pJ/bit Read Energy With 80-MHz Access for IoT Applications
2020 · Ken Matsubara, Tsutomu Nagasawa, et al. · IEEE Solid-State Circuits Letters · 3
Works count: 7
Citation count: 74
H-index: 4
I10-index: 4
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