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Author

Mahendra Rathor

Observed name: M. Rathor
ORCID: 0000-0001-8633-7322
Observed ORCID: 0000-0001-8633-7322
OpenAlex ID: A5091440578
IP Core Steganography for Protecting DSP Kernels Used in CE Systems
2019 · Anirban Sengupta, Mahendra Rathor · IEEE Transactions on Consumer Electronics · 45
Facial Biometric for Securing Hardware Accelerators
2020 · Anirban Sengupta, Mahendra Rathor · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 35
Securing Hardware Accelerators for CE Systems Using Biometric Fingerprinting
2020 · Anirban Sengupta, Mahendra Rathor · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 30
Enhanced Security of DSP Circuits Using Multi-Key Based Structural Obfuscation and Physical-Level Watermarking for Consumer Electronics Systems
2020 · Anirban Sengupta, Mahendra Rathor · IEEE Transactions on Consumer Electronics · 29
IP Core Steganography Using Switch Based Key-Driven Hash-Chaining and Encoding for Securing DSP Kernels Used in CE Systems
2020 · Mahendra Rathor, Anirban Sengupta · IEEE Transactions on Consumer Electronics · 28
Structural Obfuscation and Crypto-Steganography-Based Secured JPEG Compression Hardware for Medical Imaging Systems
2020 · Anirban Sengupta, Mahendra Rathor · IEEE Access · 28
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Hard-Sign: A Hardware Watermarking Scheme Using Dated Handwritten Signature
2023 · Mahendra Rathor, Girraj Prasad Rathor · IEEE Design and Test · 14
Obfuscated Hardware Accelerators for Image Processing Filters—Application Specific and Functionally Reconfigurable Processors
2020 · Anirban Sengupta, Mahendra Rathor · IEEE Transactions on Consumer Electronics · 12
Crypto-Based Dual-Phase Hardware Steganography for Securing IP cores
2019 · Anirban Sengupta, Mahendra Rathor · Letters of the IEEE Computer Society · 11
Security of Functionally Obfuscated DSP Core Against Removal Attack Using SHA-512 Based Key Encryption Hardware
2018 · Anirban Sengupta, Mahendra Rathor · IEEE Access · 11
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Quadruple phase watermarking during high level synthesis for securing reusable hardware intellectual property cores
2022 · Mahendra Rathor, Aditya Anshul, et al. · Computers & Electrical Engineering · 10
Revisiting Black-Hat HLS: A Lightweight Countermeasure to HLS-Aided Trojan Attack
2023 · Mahendra Rathor, Anirban Sengupta · IEEE Embedded Systems Letters · 9
Securing Reusable IP Cores Using Voice Biometric Based Watermark
2023 · Mahendra Rathor, Aditya Anshul, et al. · IEEE Transactions on Dependable and Secure Computing · 8
Exploring Handwritten Signature Image Features for Hardware Security
2022 · Mahendra Rathor, Anirban Sengupta, et al. · IEEE Transactions on Dependable and Secure Computing · 7
Protecting DSP Kernels Using Robust Hologram-Based Obfuscation
2018 · Anirban Sengupta, Mahendra Rathor · IEEE Transactions on Consumer Electronics · 6
HLS Based IP Protection of Reusable Cores Using Biometric Fingerprint
2020 · Anirban Sengupta, Mahendra Rathor · Letters of the IEEE Computer Society · 5
Design Flow of Secured N-Point DFT Application Specific Processor Using Obfuscation and Steganography
2020 · Mahendra Rathor, Anirban Sengupta · Letters of the IEEE Computer Society · 5
Robust Logic locking for Securing Reusable DSP Cores
2019 · Mahendra Rathor, Anirban Sengupta · IEEE Access · 5
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Aiding to Multimedia Accelerators: A Hardware Design for Efficient Rounding of Binary Floating Point Numbers
2023 · Mahendra Rathor, Vishesh Mishra, et al. · Design, Automation, and Test in Europe · 4
Securing IP Cores in CE Systems using Key-driven Hash-chaining based Steganography
2020 · Mahendra Rathor, Pallabi Sarkar, et al. · International Conference on Consumer Electronics · 4
Securing Hardware Accelerators Using Multi-Key Based Structural Obfuscation
2020 · Anirban Sengupta, Mahendra Rathor, et al. · Letters of the IEEE Computer Society · 4
ALOHA-FP2I: Efficient Algorithms and Hardware for Multi-Mode Rounding of Floating Point to Integer
2024 · Mahendra Rathor · ACM Transactions on Embedded Computing Systems · 3
Signature Biometric based Authentication of IP Cores for Secure Electronic Systems
2021 · Mahendra Rathor, Anirban Sengupta · IEEE International Symposium on Smart Electronic Systems (iSES) · 3
Enhanced Functional Obfuscation of DSP core using Flip-Flops and Combinational logic
2019 · Mahendra Rathor, Anirban Sengupta · International Conference on Consumer Electronics · 3
Dual-Mode Rounding Algorithms and Hardware for Posit-Based DNN Training: The Future of Mixed Precision Frameworks
2025 · Vishesh Mishra, Mahendra Rathor, et al. · ACM Transactions on Embedded Computing Systems · 2
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Works count: 46
Citation count: 330
H-index: 10
I10-index: 11
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