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Author

Vijay Sontakke

Observed institution: Intel (United States)
ORCID: 0000-0002-1443-2440
Observed ORCID: 0000-0002-1443-2440
OpenAlex ID: A5092931599
Memory built-in self-repair and correction for improving yield: a review
2023 · Vijay Sontakke, Delsikreo Atchina · International Journal of Power Electronics and Drive Systems/International Journal of Electrical and Computer Engineering · 6
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A survey of scan-capture power reduction techniques
2023 · Vijay Sontakke, John Dickhoff · International Journal of Power Electronics and Drive Systems/International Journal of Electrical and Computer Engineering · 5
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Developments in scan shift power reduction: a survey
2023 · Vijay Sontakke, John Dickhoff · Bulletin of Electrical Engineering and Informatics · 3
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Analysis of Test Access Mechanisms for Improving Scan Compression and Test Time
2025 · Vijay Sontakke · International Journal of Advanced Computer Science and Applications · 1
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Testing nanometer memories: a review of architectures, applications, and challenges
2024 · Vijay Sontakke, Delsikreo Atchina · International Journal of Power Electronics and Drive Systems/International Journal of Electrical and Computer Engineering · 1
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Improvements in Test Access Design and Scheduling for Checking Chip Manufacturing Quality
2026 · Vijay Sontakke · Journal of Electrical Systems
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Works count: 6
Citation count: 16
H-index: 3
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