Product
Help
Pricing
About
Jobs
Log in
Get started
Author
Add to collection
Pooja Beniwal
Institution:
Indraprastha Institute of Information Technology Delhi
Observed institution:
Indraprastha Institute of Information Technology Delhi
ORCID:
0009-0006-4311-1044
Observed ORCID:
0009-0006-4311-1044
OpenAlex ID:
A5094337570
Machine Learning-Driven Flip-Flop Timing Model and its Application in Resolving Marginal Timing Violations
2025
·
Pooja Beniwal
, Sneh Saurabh
, et al.
·
ACM Transactions on Design Automation of Electronic Systems
·
1
LiMo: A Framework Leveraging Machine Learning for Multi-Input Switching Timing Models of Complex Logic Gates
2025
·
Pooja Beniwal
, Sneh Saurabh
, et al.
·
IEEE Transactions on Circuits and Systems I Regular Papers
·
1
Codriver: A Tool for Coverage-Driven Functional Verification of RISC-V Processors
2024
·
Dikshant Yadav
, Priyanka Bhagat
, et al.
·
Lecture notes in electrical engineering
·
1
HAWK: Machine Learning-Driven Waiver of Marginal Hold-Time Violations with Process-Variation Awareness
2026
·
Umang Singadiya
, Pooja Beniwal
, et al.
·
International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA)
Modeling Glitches due to Multiple Input Switching using Machine Learning
2026
·
Pooja Beniwal
, Ajoy Mandal
, et al.
·
ACM Transactions on Design Automation of Electronic Systems
Artificial Neural Network-based Prediction and Alleviation of Congestion during Placement
2024
·
Pooja Beniwal
, Sneh Saurabh
·
International Conference on VLSI Design and International Conference on Embedded Systems (VLSID)
Show more works
View as search
Works count:
6
Citation count:
3
H-index:
1
I10-index:
Year
Topic
Type
