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Author

André Sintzoff

Observed names: A. Sintzoff, Sintzoff, André
Institution: Thales (France)
Observed institution: Thales (France)
ORCID: 0009-0008-5306-7811
Observed ORCID: 0009-0008-5306-7811
OpenAlex ID: A5099779202
Using a Performance Model to Implement a Superscalar CVA6
2024 · Côme Allart, Jean-Roch Coulon, et al. · ACM International Conference on Computing Frontiers: Workshops and Special Sessions (CF Companion) · 4
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Securing a RISC-V architecture: A dynamic approach
2023 · S. Pillement, M. Méndez Real, et al. · Design, Automation, and Test in Europe · 2
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Forging Robust Building Blocks for Next-Gen RISC-V Chips: Virtual Repository and IP Card
2026 · Cătălin Bogdan Ciobanu, Francesco Conti, et al. · Euromicro Conference on Digital System Design (DSD)
artecs-group/PERCIVAL: Zenodo release
2026 · Florian Zaruba, Michael Schaffner, et al. · Zenodo (CERN European Organization for Nuclear Research)
Leveraging a Superscalar CVA6 to Implement NTT Instructions for Post-Quantum Cryptography
2026 · ALLART, Côme, Guilloux, Kévin, et al. · Zenodo (CERN European Organization for Nuclear Research)
Leveraging a Superscalar CVA6 to Implement NTT Instructions for Post-Quantum Cryptography
2026 · Côme Allart, Kévin Guilloux, et al. · Lecture notes in computer science
Eliminating Write-After-Write Hazards to Improve Performance in Embedded Processors
2025 · Côme Allart, Junheng Zheng, et al. · Euromicro Conference on Digital System Design (DSD)
Works count: 7
Citation count: 6
H-index: 2
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